Prosecution Insights
Last updated: April 19, 2026
Application No. 18/773,795

APPARATUS AND METHOD FOR IMPROVING YIELD OF ADVANCED PACKAGES

Non-Final OA §112
Filed
Jul 16, 2024
Examiner
GEYER, SCOTT B
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Chipletz Inc.
OA Round
3 (Non-Final)
94%
Grant Probability
Favorable
3-4
OA Rounds
2y 1m
To Grant
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
664 granted / 706 resolved
+26.1% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
15 currently pending
Career history
721
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
21.1%
-18.9% vs TC avg
§102
42.4%
+2.4% vs TC avg
§112
24.2%
-15.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 706 resolved cases

Office Action

§112
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 20, 2025 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-6, 13, and 14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Independent claims 1 and 14, as well as dependent claim 13, recite a process of “using a manufacturing technology other than a semiconductor manufacturing technology” (emphasis added). It is wholly unclear as to what type of process, used to make a semiconductor device/package, would not be considered semiconductor manufacturing technology. In addition, neither the claims nor the specification provide any details, definitions, or explanations as to what would constitute a process other than a semiconductor manufacturing technology. Without any guidance or explanations directed to this newly added claim limitation, the claims are rejected under 35 USC 112(a) as failing to comply with the enablement requirement, since the dearth of any definition or details would not enable one of ordinary skill in the art to make and/or use the invention. Dependent claims 2-6 are also rejected as they depend from the above-rejected claim(s) and thus inherit all the deficiencies of these claims. // Claims 1, 13, and 14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1, 13, and 14 recite limitations to “using a manufacturing technology other than a semiconductor manufacturing technology”. It is unclear as to what sort of process would be identify as other than semiconductor manufacturing technology, as the claims, drawings, and specification do not define or disclose this at all Dependent claims 2-6 are also rejected as they depend from the above-rejected claim(s) and thus inherit all the deficiencies of these claims. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-6, 13, and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Independent claims 1 and 14, as well as dependent claim 13, recite a process of “using a manufacturing technology other than a semiconductor manufacturing technology” (emphasis added). It is wholly unclear as to what type of process, used to make a semiconductor device/package, would not be considered semiconductor manufacturing technology. In addition, neither the claims nor the specification provide any details, definitions, or explanations as to what would constitute a process other than a semiconductor manufacturing technology. Due to the lack of explanation or definitions, the usage of this limitations renders the claims indefinite. Dependent claims 2-6 are also rejected as they depend from the above-rejected claim(s) and thus inherit all the deficiencies of these claims. The applicant has used the term “monolithic” in claims 1, 2, 13, 14. The term monolithic, in semiconductor technology, refers to an integrated circuit that has all its components formed on the surface layer of a chip; a single piece of semiconductor. The term can also imply or refer to an integrated circuit that is manufactured within a single crystal, or a single piece of semiconductor material (commonly silicon, e.g.). The applicant appears to be conflating a multi-die semiconductor package, as a finished unitary object, with a monolithic device, which is contrary to the known accepted definition of the term, to those of ordinary skill in the art. According to MPEP 2173.05(a) III., while the applicant may be their own lexicographer, they may not ascribe a different definition to a known term absent of a specific and explicit definition within their disclosure. However, in this instant case, the applicant has not provided an explicit definition to the term; therefore, the use of such a term in the manner of which it is utilized in the claims renders the claims indefinite. Dependent claims 3-6 are also rejected as they depend from the above-rejected claim(s) and thus inherit all the deficiencies of these claims. Response to Arguments Applicant’s arguments with respect to claims 1-6, 13, and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in U.S.A. or Canada) or 571-272-1000. /SCOTT B GEYER/ Primary Examiner, Art Unit 2812
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Prosecution Timeline

Jul 16, 2024
Application Filed
Nov 06, 2024
Non-Final Rejection — §112
Feb 12, 2025
Response after Non-Final Action
Feb 12, 2025
Response Filed
Mar 13, 2025
Response Filed
Mar 25, 2025
Final Rejection — §112
Aug 20, 2025
Request for Continued Examination
Aug 21, 2025
Response after Non-Final Action
Aug 25, 2025
Response Filed
Mar 07, 2026
Non-Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.4%)
2y 1m
Median Time to Grant
High
PTA Risk
Based on 706 resolved cases by this examiner. Grant probability derived from career allow rate.

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