DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-20 of U.S. Patent No. 11,349,004 (“Yu”). Although the claims at issue are not identical, they are not patentably distinct from each other because the differences in claim language amount to either a removal of limitations not critical to the inventive concept or a rewording of already protected limitations. Below, the pending claim language is compared to the patented claim limitations. The patented claim language is italicized.
Pending Claim 1 recites a semiconductor device comprising:
a device layer comprising a first transistor structure and a second transistor structure;
Patented Claim 1 recites a semiconductor device comprising:
a first transistor structure;
a second transistor structure adjacent the first transistor structure;
a first interconnect structure on a front-side of the device layer; and
a second interconnect structure on a backside of the device layer, the second interconnect structure comprising:
a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and
a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure comprising:
a first contact electrically connected to a first source/drain region of the first transistor structure; and
a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and
a second contact electrically connected to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact, wherein a first lateral surface of the first contact is level with a second lateral surface of the second contact.
a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.
The pending claim differs from the patented claim by rewording limitations such as the wording around the first and second transistor, by removing the limitations on the first and second dielectric layer and by including the limitation that the first and second contact have a lateral surface level with each other. The first difference does not provide patentable distinction. The second difference also does not provide patentable distinction since dielectric layers can comprise a multi-layer and it would have been obvious to one of ordinary skill in the art that the contacts are surrounded by an ILD (interlayer dielectric). With regards to the third difference, it would have been obvious to one of ordinary skill in the art for at least the surfaces of the contacts, which are furthest from the first and second transistors, to have been level so as to provide a planarized surface for contacting bumps or other metallization layer.
For brevity, the dependent claims are matched with their equivalent in the cited patent without repetition of the claim language.
Pending Claim 2 is unpatentable in view of patented Claim 2.
Pending Claim 3 is unpatentable in view of patented Claims 3 & 6.
Pending Claim 4 is unpatentable in view of patented Claim 4.
Pending Claim 5 is unpatentable in view of patented Claim 5.
Pending Claim 6 is unpatentable in view of patented Claim 6.
Pending Claim 7 is unpatentable in view of patented Claim 6.
Pending Claim 8 recites a semiconductor device comprising:
a first transistor structure, the first transistor structure having a first channel length;
Patented Claim 8 recites a semiconductor device comprising:
a first transistor structure comprising a first nanostructure, a first gate structure surrounding the first nanostructure, and a first source/drain region adjacent the first gate structure, the first transistor structure having a first channel length;
a second transistor structure adjacent the first transistor structure, the second transistor structure having a second channel length greater than the first channel length;
a second transistor structure adjacent the first transistor structure, the second transistor structure comprising a second nanostructure, a second gate structure surrounding the second nanostructure, and a second source/drain region adjacent the second gate structure, the second transistor structure having a second channel length greater than the first channel length;
a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and
a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and
a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure comprising:
a first dielectric layer on the backside of the first transistor structure;
a first substrate on the backside of the second transistor structure; and
a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure comprising:
a first dielectric layer on the backside of the first transistor structure;
a first substrate on the backside of the second transistor structure; and
a second dielectric layer on a backside of the first substrate, wherein the first dielectric layer extends along sidewalls of the second dielectric layer and the first substrate.
a second dielectric layer on a backside of the first substrate, wherein a height of the first substrate and the second dielectric layer is equal to a height of the first dielectric layer.
The differences in claim language between the pending claim and the cited patent amount largely to the removal of obvious elements in the nanostructures such as an All-Around-Gate configuration. The only real distinction between the claims is the rewording of the height of the first dielectric layer is equal to the combined height of the first substrate and second dielectric layer. The rewording is not found to be patentably distinct. Absent language such as “extending partially” or “extends beyond”, claiming the first dielectric layer extends along sidewalls of the second dielectric layer and the first substrate would have created a structure such that the height of the first dielectric layer is equal to the combined height of the first substrate and second dielectric layer. Applicant makes no indication in the subsequent dependent claims that the first dielectric layer extends beyond or partially along the combined sidewalls of the second dielectric layer and the substrate.
For brevity, the dependent claims are matched with their equivalent in the cited patent without repetition of the claim language.
Pending Claim 9 is obvious in view of patented Claims 1, 3, 4 & 9.
Pending Claim 10 is obvious in view of patented Claim 8 since trench isolation was widely known at the time for providing increased isolation between electrical elements and does not appear to have any unexpected results from Applicant’s disclosure.
Pending Claim 11 is unpatentable in view of patented Claims 8 and 15.
Pending Claim 12 is unpatentable in view of patented Claim 14.
Pending Claim 13 is unpatentable in view of patented Claim 14.
Pending Claim 14 is unpatentable in view of patented Claim 10.
Pending Claim 15 recites a semiconductor device comprising:
a device layer comprising a first transistor structure and a second transistor structure;
Patented Claim 15 recites a method comprising:
forming a first transistor structure and a second transistor structure on a semiconductor substrate;
a first interconnect structure on a front-side of the device layer; and
a second interconnect structure on a backside of the device layer, the second interconnect structure comprising:
a first contact electrically connected to a first source/drain region of the first transistor structure; and
a second contact electrically connected to a second source/drain region of the second transistor structure, wherein the second source/drain region extends farther away from the first interconnect structure than the first source/drain region.
forming a first contact extending through the first dielectric layer and coupled to the first source/drain region; and
forming a second contact extending through the second dielectric layer and coupled to a second source/drain region of the second transistor structure, the second contact having a length greater than the first contact.
The pending claim differs from the patented claim by being a product that is a result of the method claimed by the patent. As the devices are linked by product and process of manufacturing the product, the device is not patentably distinct from the product made by the method of manufacturing and could have been included at the time of patenting the first patent. Additional distinctions include the removal of a first and second dielectric layer and a rewording of the source/drain heights to be reflected instead by the first and second contact height. However, a difference in source/drain heights, which too is a result of the method claimed in the cited patent, would have obviously resulted in a difference in height for the contacts since less height is needed to reach a source/drain having a greater height. As such, there is no patentable distinction between the pending claim and the protected limitations.
For brevity, the dependent claims are matched with their equivalent in the cited patent without repetition of the claim language.
Pending Claim 16 is obvious in view of patented Claims 1 & 15.
Pending Claim 17 is unpatentable in view of patented Claim 15.
Pending Claim 18 is unpatentable in view of patented Claims 1, 6 and 15.
Pending Claim 19 is unpatentable in view of patented Claim 15.
Pending Claim 20 is obvious in view of patented Claim 15 since trench isolation was widely known at the time for providing increased isolation between electrical elements and does not appear to have any unexpected results from Applicant’s disclosure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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