DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 is objected to because of the following informalities: claim 5, line 4 contains the phrase, “wherein top ends of the sidewall portions is in physical contact with the first via,” when it should be wherein top ends of the sidewall portions are in physical contact with the first via. Appropriate correction is required.
Claims 15-17 are objected to because of the following informalities: claim 15, line 10 contains the phrase, “firsts straight line,” when it should be first straight line. Appropriate correction is required. Claims 16 and 17 are objected to due to their dependency on claim 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 15 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cosemans et al. (United States Patent Application Publication No. US 2017/0062421 A1, hereinafter “Cosemans”).
In reference to claim 15, Cosemans discloses a structure which meets the claim. Fig. 1-4b of Cosemans discloses a structure that comprises dielectric isolation regions (116), a semiconductor strip (portion of 115 within 116) in the dielectric isolation regions (116), a semiconductor fin (portion of 115 above 116) that overlaps and is joined to the semiconductor strip (portion of 115 within 116). A gate stack (101) is over the semiconductor fin (portion of 115 above 116). Fig. 1 and 3 shows that a first source/drain region (120) and second source/drain region (120) aside of the gate stack (101). A source/drain contact plug (151) is between, and electrically connected to, the first source/drain region (120) and the second source/drain region (120), wherein in a top view of the structure, the first source/drain region (120), the source/drain contact plug (151), and the second source/drain region (120) are aligned to a first straight line that is parallel to a first lengthwise direction of the gate stack (110). There is a buried metal track (130) comprising a first portion directly underlying the gate stack (110) and a second portion directly underlying the source/drain contact plug (151), wherein in the top view, the buried metal track (130) is a continuous strip that has a second lengthwise direction perpendicular to the first lengthwise direction.
In reference to claim 18, Cosemans discloses a structure which meets the claim. Fig. 1-4b of Cosemans discloses a structure that comprises an isolation region (116). A semiconductor strip (portion of 115 within 116) is in the isolation region (116). There is a buried conductive track (130, 140) having a lengthwise direction parallel to a lengthwise direction of the semiconductor strip (portion of 115 within 116). A semiconductor fin (portion of 115 above 116) overlaps the semiconductor strip (portion of 115 within 116). There is a source/drain region (120). Although not illustrated, Cosemans discloses a source/drain silicide (p. 1, paragraph 12) on a sidewall of the source/drain region (120). A source/drain contact plug (151) contacts the source/drain silicide such that the source/drain contact plug (151) overlaps and is electrically connected to the buried conductive track (130, 140). A gate electrode (101) crosses over the buried conductive track (130, 140) and the semiconductor fin (portion of 115 above 116). The gate electrode (101) is electrically connected to the source/drain region (120) through the buried conductive track (130, 140) and the source/drain contact plug (151) since they are part of the same transistor.
With regard to claim 19, there is a dielectric layer (134) comprising a bottom portion overlapped by the buried conductive track (130, 140) and sidewall portions forming a ring encircling the buried conductive track (130, 140).
In reference to claim 20, fig. 3 of Cosemans shows that the buried conductive track (130, 140) is a part of the Front End of Line Layer or FEOL (160). Cosemans discloses (p. 3, paragraph 30) the use of metals in the formation of the Front End of Line Layer or FEOL (160) thus meeting the claim.
Allowable Subject Matter
Claims 1-4 and 6-14 are allowed.
Claim 5 would be allowable if the language of the claim is corrected (see above section titled Claim Objections).
Claims 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims AND if the language of the base claim is corrected (see above section titled Claim Objections).
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a structure which comprises an elongated gate stack with a gate electrode over a gate dielectric that extends in a first direction, an elongated semiconductor fin which extends in a second direction perpendicular to the first direction, a first source/drain region aside the gate stack, an elongated buried metal track that that extends in a direction parallel to the second direction in combination with the specific first and second via structures described by the applicant in claim 1. In the examiner’s opinion, it would also not be obvious to implement a structure which comprises a semiconductor strip in dielectric isolation regions, a semiconductor fin that overlaps and joins the semiconductor strip, a gate stack over the semiconductor fin, first and second source/drains region aside the gate stack with a source/drain contact plug that is between and electrically connected to them such that they are aligned in a direction parallel to a length direction of the gate stack, a buried metal track that extends in a direction perpendicular to the length direction of the gate stack while having portions directly underlying the gate stack and the source/drain contact plug in combination with the specific first and second via structures described by the applicant in claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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