Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/16/24, 10/25/24, 04/17/25 were filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims #1-5, 7-10, 12, 13, 15, 16, 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims #1-5, 7, 10, 11 of Lin et al., (U.S. Patent No. U.S. 11,600,717), hereinafter referred to as "Lin". Although the claims at issue are not identical, they are not patentably distinct from each other because;
Claim #1 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #1 of U.S. Patent No. 11,257,805, which discloses, a method comprising: forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions; forming a dielectric dummy strip between the isolation regions; recessing the isolation regions, so that some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin; etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin; and forming a gate stack on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #1, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #1 of the instant application, which states, a method comprising: forming isolation regions in a semiconductor substrate; forming protruding semiconductor fins between the isolation regions; forming a dielectric dummy strip laterally between the isolation regions, wherein a top portion of the dielectric dummy strip forms a dielectric dummy fin that is higher than the isolation regions; performing an etching process on the dielectric dummy strip using an etching chemical; and after the etching process, forming a gate stack over the protruding semiconductor fins.
Claim #2 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #2 of U.S. Patent No. 11,257,805, which discloses, a method wherein during the etching the dielectric dummy strip, the protruding semiconductor fins are exposed to an etching chemical used for the etching. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #2, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #2 of the instant application, which states, a method wherein in the etching process, a top surface and upper parts of sidewalls of the dielectric dummy strip are exposed to the etching chemical.
Claim #3 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #1 of U.S. Patent No. 11,257,805, which discloses, a method comprising: forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions; forming a dielectric dummy strip between the isolation regions; recessing the isolation regions, so that some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin; etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin; and forming a gate stack on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #1, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #3 of the instant application, which states, a method wherein before the etching process, the dielectric dummy strip has a first top width and a bottom width, and wherein after the etching process, the dielectric dummy strip has a second top width smaller than the first top width.
Claim #4 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #3 of U.S. Patent No. 11,257,805, which discloses, a method wherein during the etching the dielectric dummy strip, the protruding semiconductor fins are protected by an etching mask. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #3, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #4 of the instant application, which states, a method further comprising: forming an etching mask to cover the protruding semiconductor fins, wherein the etching process is performed using the etching mask to protect the protruding semiconductor fins from being etched.
Claim #5 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #2 of U.S. Patent No. 11,257,805, which discloses, a method wherein during the etching the dielectric dummy strip, the protruding semiconductor fins are exposed to an etching chemical used for the etching. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #2, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #5 of the instant application, which states, a method wherein during the etching process, the protruding semiconductor fins are exposed to the etching chemical.
Claim #7 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #11 of U.S. Patent No. 11,257,805, which discloses, a method wherein after the etching, the dielectric dummy fin has a tapered profile with upper portions narrower than respective lower portions. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #11, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #7 of the instant application, which states, a method wherein before the etching process, the dielectric dummy fin is tapered, with upper portions wider than respective lower portions, and wherein after the etching process, the dielectric dummy fin is tapered, with upper portions narrower than respective lower portions.
Claim #8 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #4 of U.S. Patent No. 11,257,805, which discloses, a method further comprising: etching the gate stack to form an opening, wherein the opening separates the gate stack into two portions, and the dielectric dummy fin is underlying and revealed through the opening; and filling a dielectric material into the opening to form a gate isolation region. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #4, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #8 of the instant application, which states, a method further comprising: etching the gate stack to form an opening, wherein the opening separates the gate stack into two portions, and the dielectric dummy fin is underlying and revealed through the opening; and filling a dielectric material into the opening to form a gate isolation region.
Claim #9 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #5 of U.S. Patent No. 11,257,805, which discloses, a method further comprising: removing the two portions of the gate stack to form trenches; and forming replacement gate stacks in the trenches. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #5, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #9 of the instant application, which states, a method further comprising: removing the two portions of the gate stack to form trenches; and forming replacement gate stacks in the trenches.
Claim #10 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #1 and 11 of U.S. Patent No. 11,257,805. Wherein claim #1 discloses, a method comprising: forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions; forming a dielectric dummy strip between the isolation regions; recessing the isolation regions, so that some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin; etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin; and forming a gate stack on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin. Furthermore, claim #11 discloses, wherein after the etching, the dielectric dummy fin has a tapered profile with upper portions narrower than respective lower portions. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #1 and 11, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #10 of the instant application, which states, a method wherein before the etching process, a first top surface of the dielectric dummy fin is coplanar with second top surfaces of the protruding semiconductor fins, and wherein after the etching process, the first top surface of the dielectric dummy fin is lower than the second top surfaces of the protruding semiconductor fins.
Claim #12 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #1 of U.S. Patent No. 11,257,805, which discloses, a method comprising: forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions; forming a dielectric dummy strip between the isolation regions; recessing the isolation regions, so that some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin; etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin; and forming a gate stack on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #1, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #12 of the instant application, which states, a method comprising: forming shallow trench isolation regions in a semiconductor substrate, wherein a first semiconductor strip and a second semiconductor strip are formed between neighboring ones of the shallow trench isolation regions; replacing the first semiconductor strip with a dielectric dummy strip; recessing the shallow trench isolation regions, wherein top portions of the dielectric dummy strip and the second semiconductor strip form a dummy dielectric fin and a protruding semiconductor fin, respectively, and wherein the dummy dielectric fin has a first top width; reducing the first top width of the dielectric dummy strip to a second top width; and forming a gate stack on the dummy dielectric fin and the protruding semiconductor fin.
Claim #13 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #1 and 2 of U.S. Patent No. 11,257,805. Wherein claim #1 discloses, a method comprising: forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions; forming a dielectric dummy strip between the isolation regions; recessing the isolation regions, so that some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin; etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin; and forming a gate stack on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin. Furthermore, claim #2 discloses, wherein during the etching the dielectric dummy strip, the protruding semiconductor fins are exposed to an etching chemical used for the etching. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #1 and 2, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #13 of the instant application, which states, a method wherein the reducing the first top width comprises performing an etching process on the dummy dielectric fin and the protruding semiconductor fin.
Claim #15 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #10 of U.S. Patent No. 11,257,805, which discloses, a method wherein the etching the dielectric dummy fin is performed using a wet etching process. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #10, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #15 of the instant application, which states, a method wherein the etching the dielectric dummy fin is performed using a wet etching process.
Claim #16 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #2 of U.S. Patent No. 11,257,805, which discloses, a method wherein during the etching the dielectric dummy strip, the protruding semiconductor fins are exposed to an etching chemical used for the etching. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #2, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #16 of the instant application, which states, a method wherein the reducing the first top width of the dielectric dummy strip is performed through an etching process using an etching chemical, and wherein during the etching process, the protruding semiconductor fin is exposed to the etching chemical.
Claim #18 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #1 and 7 of U.S. Patent No. 11,257,805. Wherein claim #1 discloses, a method comprising: forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions; forming a dielectric dummy strip between the isolation regions; recessing the isolation regions, so that some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin; etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin; and forming a gate stack on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin. Furthermore, claim #7 discloses, wherein before the etching the dielectric dummy fin, the top width of the dielectric dummy fin is greater than the bottom width of the dielectric dummy fin, and the top width is reduced by the etching the dielectric dummy fin more than the bottom width. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #1 and 7, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #18 of the instant application, which states, a method comprising: forming shallow trench isolation regions in a semiconductor substrate; forming a semiconductor strip and a dielectric dummy strip laterally between neighboring ones of the shallow trench isolation regions; recessing the shallow trench isolation regions, wherein top portions of the dielectric dummy strip and the semiconductor strip form a dummy dielectric fin and a protruding semiconductor fin, respectively, wherein the dummy dielectric fin has a first top width; performing an etching process to etch the dielectric dummy fin, wherein the etching process results in the first top width of the dielectric dummy fin to be reduced by a first width difference, and wherein the etching process results in a second top width of the protruding semiconductor fin to be reduced by a second width difference smaller than the first width difference; and forming a gate stack contacting the dummy dielectric fin.
Claim #19 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #2 of U.S. Patent No. 11,257,805, which discloses, a method wherein during the etching the dielectric dummy strip, the protruding semiconductor fins are exposed to an etching chemical used for the etching. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #2, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #19 of the instant application, which states, a method wherein during the etching process, the protruding semiconductor fin is also etched.
Claim #20 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #3 of U.S. Patent No. 11,257,805, which discloses, a method wherein during the etching the dielectric dummy strip, the protruding semiconductor fins are protected by an etching mask. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #3, of U.S. Patent No. 11,257,805, produces the same semiconductor structure as that in claim #20 of the instant application, which states, a method wherein during the etching process, the protruding semiconductor fin is protected by an etching mask from being etched.
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Claim #6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims #1 of Lin et al., (U.S. Patent No. U.S. 11,600,717), hereinafter referred to as "Lin" as shown in the rejection of claim #1 above and in view of Cheng et al., (U.S. Pat. No. 2020/0357896), hereinafter referred to as “Cheng”.
Lin substantially shows the claimed invention as shown in the rejection claim #1 above.
Lin with respect to claim #6, fails to show wherein during the etching process, the protruding semiconductor fins have a lower etching rate than the dielectric dummy fin.
Cheng teaches, with respect to claim #6, a method wherein during the etching process, the protruding semiconductor fins have a lower etching rate than the dielectric dummy fin (paragraph 0055-0056).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #6, to modified the invention of Lin, with the modifications taught by Cheng invention, which teaches, a method wherein during the etching process, the protruding semiconductor fins have a lower etching rate than the dielectric dummy fin, to incorporate a structure that allows the removal of the dummy fins without damaging the stationary fins, as taught by Cheng.
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Claim #11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims #1 of Lin et al., (U.S. Patent No. U.S. 11,600,717), hereinafter referred to as "Lin" as shown in the rejection of claim #1 above and in view of Cheng et al., (U.S. Pat. No. 2017/0338323), hereinafter referred to as “Cheng(2)”.
Lin substantially shows the claimed invention as shown in the rejection claim #1 above.
Lin, with respect to claim #11, fails to show wherein during the etching process, the protruding semiconductor fins have a lower etching rate than the dielectric dummy fin.
Cheng(2)teaches, with respect to claim #11, a method wherein the dielectric dummy strip comprises silicon oxide (paragraph 0046).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #6, to modified the invention of Lin, with the modifications taught by Cheng(2) invention, which teaches, a method wherein the dielectric dummy strip comprises silicon oxide, to incorporate a structure that allows the removal of the dummy fins without damaging the stationary fins, as taught by Cheng(2).
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Claim #14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims #1 and 2 of Lin et al., (U.S. Patent No. U.S. 11,600,717), hereinafter referred to as "Lin" as shown in the rejection of claim #13 above and in view of SU et al., (U.S. Pat. No. 2019/0088762), hereinafter referred to as “Su”.
Lin substantially shows the claimed invention as shown in the rejection claim #13 above.
Lin with respect to claim #14, fails to show wherein during the etching process, the protruding semiconductor fins have a lower etching rate than the dielectric dummy fin.
Su teaches, with respect to claim #14, a method wherein during the etching process, the protruding semiconductor fins have a lower etching rate than the dielectric dummy fin (paragraph 0027).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #14, to modified the invention of Lin, with the modifications taught by Su invention, which teaches, a method wherein during the etching process, the protruding semiconductor fins have a lower etching rate than the dielectric dummy fin, to incorporate a method so as to protect the ILD layer from being damaged, as taught by Su.
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Claim #17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims #2 of Lin et al., (U.S. Patent No. U.S. 11,600,717), hereinafter referred to as "Lin" as shown in the rejection of claim #16 above and in view of Cheng et al., (U.S. Pat. No. 2020/0357896), hereinafter referred to as “Cheng”.
Lin substantially shows the claimed invention as shown in the rejection claim #16 above.
Lin, with respect to claim #17, fails to show wherein during the etching process, the protruding semiconductor fin has a lower etching rate than the dielectric dummy fin.
Cheng teaches, with respect to claim #17, a wherein during the etching process, the protruding semiconductor fin has a lower etching rate than the dielectric dummy fin (paragraph 0055-0056).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #17, to modified the invention of Lin, with the modifications taught by Cheng invention, which teaches, a method wherein during the etching process, the protruding semiconductor fin has a lower etching rate than the dielectric dummy fin, to incorporate a structure that allows the removal of the dummy fins without damaging the stationary fins, as taught by Cheng.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683. The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2816
07/10/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
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