DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 7/16/2024, 3/6/2025 and 6/17/2025 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b). The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DISPLAY DEVICE COMPRISING LANE NOT OVERLAPPING CONDUCTIVE PATTERNS
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Heo et al. US PGPub. 2023/0122457.
Regarding claim 1, Heo teaches a display device (PNL, fig. 3) [0065] comprising: a pixel circuit layer (PCL, fig. 9) [0133] on a base layer (SUB, fig. 9) [0068] and comprising conductive patterns (CP, fig. 9) [0135] configuring at least one of a transistor (T1, fig. 9) [0085], a capacitor, or a signal line; a first electrode (ELT1, fig. 9) [0079] and a second electrode (ELT2, fig. 9) [0079] on the pixel circuit layer (CPL) and spaced from each other; a bank (BNK, fig. 9) [0103] on the first electrode (ELT1) and the second electrode (ELT2) and including an opening (EMA/OPN2, fig. 7) [0104]-[0105]; and light emitting elements (LD, fig. 7 and 9) [0048] between the first electrode (ELT1) and the second electrode (ELT2) in the opening (OPN2) of the bank (BNK), wherein in the opening (OPN2) of the bank (BNK), a space (D2, fig. 7 and 9) between the first electrode (ELT1) and the second electrode (ELT2) that are spaced from each other by a distance (D2, fig. 7 and 9) corresponding to a length (L, fig. 7 and 9) of the light emitting elements (LD) is defined as a lane (D2, fig. 9) in which the light emitting elements (LD) are located, and in a plan view, the lane (D2) does not overlap the conductive patterns (CP or TE1, TE2 and PL2, fig. 9) of the pixel circuit layer (CPL) and is spaced from the conductive patterns (TE2) by a distance (DIST, see examiner’s fig. 1) (Heo et al., fig. 7 and 9).
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Examiner’s Fig. 1 Heo does not explicitly teach the exact dimensions of the distance or teach that the lane (D2) does not overlap the conductive patterns (CP or TE1, TE2 and PL2, fig. 9) of the pixel circuit layer (PCL) and is spaced from the conductive patterns (TE2) by a distance (DIST, see examiner’s fig. 1) equal to or greater than half of the length (L) of the light emitting elements (LD). Although Heo does not indicate that the drawing is to scale, Heo teaches (see fig. 9) that length (L) of the light emitting elements (LD) is 3-5µm [0121] and that L is greater than D2. Therefore, from fig. 9 and examiner’s fig. 1, DIST is greater than D2 and L. Hence, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill that DIST is greater than half of the length (L) of the light emitting elements (LD) since DIST is obviously greater than L. Accordingly, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use the distance in the range as claimed, because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05. Regarding claim 2, Heo teaches the display device according to claim 1, wherein the length (L) of the light emitting elements (LD) is about 10 μm or less (3-5µm, [0121]) and in a plan view, the lane (D2) is spaced from the conductive patterns (TE2) by a distance (DIST) of about 6 μm or more (DIST obviously greater than 3-5µm, [0121]) (Heo et al., fig. 9, [0121]).
Regarding claim 3, Heo teaches the display device according to claim 1, wherein the pixel circuit layer (PCL) further comprises insulating layers (ILD 1 and ILD2, fig. 9) [0135], some of the conductive patterns (TE1, TE2, fig. 9) are interconnected through a contact hole (CH1, fig. 9) passing through a portion of the insulating layers (ILD1 and ILD2), and in a plan view, the lane (D2) is spaced from all contact holes (CH1) by a distance (DIST2, examiner’s fig. 1) equal to or greater than half of the length (L) of the light emitting elements (LD) (Heo et al., fig. 9, [0121]). Heo teaches (see fig. 9) that length (L) of the light emitting elements (LD) is 3-5µm [0121] and that L is greater than D2. Therefore, from fig. 9 and examiner’s fig. 1, DIST2 is greater than D2 and L. Hence, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill that DIST2 is greater than half of the length (L) of the light emitting elements (LD) since DIST2 is obviously greater than L. Regarding claim 12, Heo teaches the display device according to claim 1, further comprising: connection electrodes (CNE1 and CNBE2, fig. 9) [0103] on the light emitting elements (LD), wherein the lane (D2) comprises a first lane, a second lane, a third lane, and a fourth lane (D2 for each of the seven LD shown in fig. 7) that are spaced from each other in the opening (OPN2) of the bank (BNK), wherein the light emitting elements (LD) comprise first light emitting elements in the first lane, second light emitting elements in the second lane, third light emitting elements in the third lane, and fourth light emitting elements in the fourth lane (first four of the seven LD shown in fig. 7), and wherein the first to fourth light emitting elements (LD) are electrically connected in series [0217] through the connection electrodes (CNE1 and CNE2, fig. 7) (Heo et al. fig. 7, [0217]). Regarding claim 14, Heo teaches the display device according to claim 1, further comprising: color conversion particles (not shown, [0201]) on the light emitting elements (LD) and converting a wavelength of light of the light emitting elements (LD); and a color filter (not shown, [0201]) on the color conversion particles (Heo et al., [0201]).
Allowable Subject Matter
Claims 4-11, 13 and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a display device comprising “sub-pixels each including the lane, wherein the conductive patterns comprise a first line extending in a second direction, and from among the sub-pixels, a first sub-pixel and a second sub-pixel adjacent in a first direction with the first line interposed therebetween are symmetric with each other with respect to the first line in a plan view” as recited in claim 4 in combination with the rest of the limitations of claim 1; a display device wherein “the conductive patterns comprises: a first auxiliary power line extending in a first direction; and a first capacitor and a second capacitor spaced in a second direction with the first auxiliary power line interposed therebetween in a plan view, wherein the first capacitor and the second capacitor are electrically connected in parallel” as recited in claim 11 in combination with the rest of the limitations of claim 1;
a display device wherein “a portion of the connection electrodes comprises a closed loop” as recited in claim 13 in combination with the rest of the limitations of claims 1 and 12; a display device wherein “the conductive patterns comprise a first auxiliary power line extending in a first direction, and in a plan view, the lane of a sub-pixel is in an area that is different from the transistor and the capacitor of the pixel circuit layer of the sub-pixel based on the first auxiliary power line” as recited in claim 15 in combination with the rest of the limitations of claim 1;
a display device comprising “a first sub-pixel and a second sub-pixel, each of the first sub-pixel and the second sub-pixel comprising the lane, wherein the conductive patterns comprise first lines extending in a second direction, and wherein the first sub-pixel and the second sub-pixel that are adjacent to two of the first lines interposed therebetween are symmetric with each other with respect to the two of the first lines in a plan view” as recited in claim 16 in combination with the rest of the limitations of claim 1; and
a display device comprising “sub-pixels, each of the sub-pixels comprising the lane, wherein the conductive patterns comprise first lines extending in a second direction, from among the sub-pixels, a first sub-pixel and a second sub-pixel adjacent with one of the first lines interposed therebetween are symmetric with each other with respect to the first line in a plan view, and at least two of the first lines are connected to one pad” as recited in claim 18 in combination with the rest of the limitations of claim 1.
Claims 5-10 and 17 are also objected to as allowable for further limiting and depending upon allowable claims 4 and 16. Claims 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a display device comprising “a signal line extending in a second direction between a pair of adjacent sub-pixels from among the sub-pixels,… wherein the pair of adjacent sub-pixels are commonly connected to the signal line and are symmetric with each other with respect to the signal line” in combination with “light emitting elements in a lane between the first electrode and the second electrode, a conductive pattern that is not in the lane” as recited in claim 19.
Claim 20 is also allowed for further limiting and depending upon allowed claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Oh et al. US PGPub. 2022/0392923 teaches a display device (fig. 16A) comprising light emitting elements between first and second electrode but the lane overlaps conductive patterns of the pixel circuit. Lee US PGPub. 2022/0238559 teaches a display device (fig. 9 ) comprising light emitting elements between first and second electrode and the lane not overlapping conductive patterns of the pixel circuit but fails to provide any dimensions of the distance and length of the light emitting elements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
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