Prosecution Insights
Last updated: October 01, 2026
Application No. 18/774,843

PACKAGE STRUCTURE

Non-Final OA §112
Filed
Jul 16, 2024
Priority
Oct 30, 2019 — provisional 62/928,347 +2 more
Examiner
CHANG, JAY C
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
582 granted / 682 resolved
+25.3% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
30 currently pending
Career history
705
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
41.6%
+1.6% vs TC avg
§102
28.2%
-11.8% vs TC avg
§112
27.7%
-12.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 682 resolved cases

Office Action

§112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 7/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 7-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 recites the limitation “wherein an interface between the first semiconductor die substantially levels with an interface between the first insulating encapsulation and the second insulating encapsulation” in lines 9-10 of the claim, which is indefinite and unclear, because the language “an interface between the first semiconductor die” only specifies the first semiconductor die, but does not specify any other element which forms the claimed “interface” with the first semiconductor die. An “interface” requires two structural elements to form the interface. One structural element by itself cannot form an interface. Thus, it is unclear what is necessarily required by the claim limitation. Note the dependent claims 8-13 necessarily inherit the indefiniteness of the claims on which they depend. Allowable Subject Matter Claims 1-6 and 14-20 are allowed. Regarding independent claim 1, Figure 11 of Son et al. (US 2015/0255426 A1, hereinafter “Son”) discloses a package structure, comprising: a first semiconductor die 111 (“semiconductor dies”- ¶0017); a first insulating encapsulation 13 (“underfill”- ¶0029); a bonding film 15 (“encapsulant”- ¶0041) disposed on the first insulating encapsulation 13, wherein the first insulating encapsulation 13 and the bonding film 15 laterally encapsulate the first semiconductor die 111, and sidewall surfaces of the first semiconductor die 111 is in direct contact with the first insulating encapsulation 13 and the bonding film 15. Son does not expressly disclose the package structure further comprising a second semiconductor die disposed on the first semiconductor die and the bonding film and a second insulating encapsulation laterally encapsulating the second semiconductor die, wherein a thickness of the first semiconductor die substantially equals to a sum of a thickness of the first insulating encapsulation and a thickness of the bonding film. Thus, regarding independent claim 1, the claim is allowed, because the prior art of record including Son, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a second semiconductor die disposed on the first semiconductor die and the bonding film” and “a second insulating encapsulation laterally encapsulating the second semiconductor die, wherein a thickness of the first semiconductor die substantially equals to a sum of a thickness of the first insulating encapsulation and a thickness of the bonding film”. Claims 2-6 are allowed as being dependent on allowed claim 1. Regarding independent claim 14, Figure 11 of Son discloses a package structure, comprising: a first semiconductor die 111 (“semiconductor dies”- ¶0017) comprising a first bonding structure; a first insulating encapsulation 13 (“underfill”- ¶0029); a bonding film 15 (“encapsulant”- ¶0041) stacked on the first insulating encapsulation 13, wherein the first insulating encapsulation 13 and the bonding film laterally 15 encapsulate the first semiconductor die 111. Son does not expressly disclose the package structure further comprising a second semiconductor die comprising a second bonding structure and a second insulating encapsulation laterally encapsulating the second semiconductor die, wherein an interface between the first bonding structure and the second bonding structure substantially levels with an interface between the second insulating encapsulation and the bonding film. Thus, regarding independent claim 14, the claim is allowed, because the prior art of record including Son, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a second semiconductor die comprising a second bonding structure” and “a second insulating encapsulation laterally encapsulating the second semiconductor die, wherein an interface between the first bonding structure and the second bonding structure substantially levels with an interface between the second insulating encapsulation and the bonding film”. Claims 15-20 are allowed as being dependent on allowed claim 14. Regarding independent claim 7, due to the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, issues as detailed above it is unclear what is necessarily required by the claim and thereby, it is unclear whether the claim at this time includes allowable subject matter. The 112 issues need to be addressed first before a determination of allowability of independent claim 7 can be made. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Jha et al. (US 10,121,722 B1), which discloses a package structure comprising a first semiconductor die laterally encapsulated by a first insulating encapsulation and a bonding film. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jul 16, 2024
Application Filed
Sep 17, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751314
DIE PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
3y 7m to grant Granted Sep 29, 2026
Patent 12751113
SEMICONDUCTOR DEVICE
2y 11m to grant Granted Sep 29, 2026
Patent 12751279
SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE
3y 0m to grant Granted Sep 29, 2026
Patent 12745667
ELECTRONIC CIRCUIT PACKAGE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE HAVING ELECTRONIC CIRCUIT PACKAGE
3y 5m to grant Granted Sep 22, 2026
Patent 12740435
METHOD OF MANUFACTURING AN INTERPOSER PRODUCT
3y 4m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+13.9%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 682 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month