Prosecution Insights
Last updated: August 17, 2026
Application No. 18/775,081

SELECTIVE DEPOSITION OF LINER LAYER

Non-Final OA §102§103§112
Filed
Jul 17, 2024
Examiner
LUKE, DANIEL M
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Applied Materials Inc.
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
499 granted / 701 resolved
+3.2% vs TC avg
Strong +19% interview lift
Without
With
+18.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
21 currently pending
Career history
725
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
49.8%
+9.8% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
21.8%
-18.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 701 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This office action is in response to the application filed 7/17/2024. Currently, claims 1-20 are pending. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 6, 12 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Both claims 6 and 18 recite “wherein a ratio of the liner [/conformal] layer on the sidewall surface to the carbon surface is about 10:1 or greater”. There is no qualitative limitation for which a ratio might be derived. In other words, a liner layer itself cannot be calculated in a ratio, but rather some quality about the liner layer (length, thickness, etc.) could be. For purposes of examination, it is presumed that the ratio is that of the relative thickness of the liner on the different surfaces. Claim 12 recites the limitation “the etching”, which lacks antecedent basis in the claims. Considering “etching” is defined in claim 8, it would appear that claim 12 should instead depend on claim 8. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5, 7, 13, 16-17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 11,316,023). Pertaining to claim 1, Huang shows, with reference to FIG. 9-10, a method of depositing a liner layer (132) on a semiconductor device, the method comprising: depositing a carbon layer (129) comprising carbon (col. 8, lines 17-20) on a substrate of the semiconductor device, the substrate having at least one feature (204) including a sidewall surface and a bottom surface, the carbon layer defining at least a portion of the bottom surface (FIG. 9) and having a carbon surface; and selectively depositing the liner layer (132) on the sidewall surface over the carbon surface (col. 8, lines 49-52). Pertaining to claims 2 and 3, Huang shows the liner layer may be silicon nitride (Si3N4) (col. 8, lines 61-65). Pertaining to claims 2 and 4, Huang shows the liner layer may be aluminum oxide, hafnium oxide, or titanium oxide (col. 8, lines 61-65). Pertaining to claim 5, Huang shows substantially no liner layer is deposited on the carbon surface (col. 9, lines 8-9). Pertaining to claim 7, Huang shows a thickness of the carbon layer is 0.5 to 15 nm (col. 8, lines 20-23), which range is nearly entirely within the claimed range. Pertaining to claim 13, Huang shows the carbon layer is deposited using a bottom up gap fill process (col. 7, line 67 – col. 8, line 3). Pertaining to claim 16, Huang shows method of depositing a conformal layer (132) on a semiconductor device, the method comprising: depositing a carbon layer (129) comprising carbon (col. 8, lines 17-20) in a bottom second portion of a substrate feature (204) selectively over a top first portion of the substrate feature (col. 7, line 67 – col. 8, line 12), the top first portion having a sidewall surface and a bottom, the carbon layer having a carbon surface that defines the bottom of the top first portion (FIG. 9); etching the carbon surface (col. 9, lines 19-22); and depositing the conformal layer (132) on the sidewall surface of the top first portion, the conformal layer deposited on the sidewall surface selectively over the carbon surface (col. 8, lines 49-52), and the conformal layer comprising one or more of a nitride or a metal oxide (col. 8, lines 61-65). Pertaining to claim 17, Huang shows the conformal layer is selected from the group consisting of silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, titanium oxide, silicon oxynitride, silicon oxycarbonitride, and combinations thereof (col. 8, lines 61-65). Pertaining to claim 19, Huang shows a thickness of the carbon layer is 0.5 to 15 nm (col. 8, lines 20-23), which range is nearly entirely within the claimed range. Pertaining to claim 20, Huang shows the etching comprises plasma etching (col. 9, lines 20-21). Claims 1-2, 4-14 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maes et al. (US 11,145,506). Pertaining to claim 1, Maes shows, with reference to FIG. 10B, a method of depositing a liner layer (2502) on a semiconductor device, the method comprising: depositing a carbon layer (2504) comprising carbon (col. 11, lines 20-30) on a substrate of the semiconductor device, the substrate having at least one feature including a sidewall surface and a bottom surface, the carbon layer defining at least a portion of the bottom surface (FIG. 10B) and having a carbon surface; and selectively depositing the liner layer (2502) on the sidewall surface over the carbon surface (col. 12, lines 13-21; col. 33, lines 1-5; FIG. 10B). Pertaining to claims 2 and 4, Maes shows the liner layer may be aluminum oxide, hafnium oxide, or titanium oxide (col. 12, lines 17-21). Pertaining to claim 5, Maes shows substantially no liner layer is deposited on the carbon surface (col. 10, lines 13-14). Pertaining to claim 6, Maes shows a ratio of the liner layer on the sidewall surface to the carbon surface is about 10:1 or greater (col. 9, line 63 – col. 10, line 4). Pertaining to claim 7, Maes shows a thickness of the carbon layer is in a range of from about 1 nm to about 100 nm (col. 10, lines 34-38). Pertaining to claim 8, Maes shows etching the carbon surface before depositing the liner layer (FIG. 10B, col. 11, line 57 – col. 12, line 12 and line 65 – col. 13, line 14). Pertaining to claim 9, Maes shows the etching is plasma etching (col. 24, line 65 – col. 25, line 8). Pertaining to claim 10, Maes shows the etching may employ hydrogen plasma (col. 24, line 65 – col. 25, line 8), and thus terminal hydrogen groups would be expected. Pertaining to claim 11, Maes shows the etching removes at least a portion of the carbon layer from the sidewall surface and a top surface of the at least one or more feature (col. 32, line 64 – col. 33, line 8; col. 24, line 65 – col. 25, line 8; FIG. 10B). Pertaining to claim 12, total removal of the carbon layer from the sidewall surface of the dielectric would necessarily be a removal of less than 90% of the original thickness in the other areas when the ratio of deposited thicknesses are within the ranges taught in col. 10, lines 38-46 of Maes. Pertaining to claim 13, Maes shows the carbon layer is deposited using a bottom up gap fill process (col. 11, lines 9-13). Pertaining to claim 14, Maes shows etching back the carbon layer to form the carbon layer selectively on the bottom surface over the sidewall surface and a top surface of the at least one feature (col. 12, lines 7-11). Pertaining to claim 16, Maes shows a method of depositing a conformal layer (2502) on a semiconductor device, the method comprising: depositing a carbon layer (2504) comprising carbon (col. 11, lines 20-30) in a bottom second portion of a substrate feature selectively over a top first portion of the substrate feature (col. 11, lines 9-13), the top first portion having a sidewall surface and a bottom, the carbon layer having a carbon surface that defines the bottom of the top first portion (FIG. 10B); etching the carbon surface (col. 30, lines 12-16); and depositing the conformal layer (2502) on the sidewall surface of the top first portion, the conformal layer deposited on the sidewall surface selectively over the carbon surface (col. 30, lines 16-18), and the conformal layer comprising one or more of a nitride or a metal oxide (col. 12, lines 17-21). Pertaining to claim 17, Maes shows the conformal layer is selected from the group consisting of silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, titanium oxide, silicon oxynitride, silicon oxycarbonitride, and combinations thereof (col. 12, lines 17-21). Pertaining to claim 18, Maes shows a ratio of the liner layer on the sidewall surface to the carbon surface is about 10:1 or greater (col. 9, line 63 – col. 10, line 4). Pertaining to claim 19, Maes shows a thickness of the carbon layer is in a range of from about 1 nm to about 100 nm (col. 10, lines 34-38). Pertaining to claim 20, Maes shows the etching is plasma etching (col. 24, line 65 – col. 25, line 8). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over either one of Huang or Maes. Huang and Maes each show the method of claim 1, but fail to show the carbon layer comprises non-porous carbon. However, porous and non-porous are the only two possibilities for the relative porosity of the carbon layer. In such instances, the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wojtecki et al. (US 2023/0178432), Lee et al. (US 12,538,773), Chawla et al. (US 10,497,613), and Huang et al. (US 11,251,305) disclose methods similar to Applicant’s. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL LUKE/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Jul 17, 2024
Application Filed
Jul 24, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
90%
With Interview (+18.7%)
2y 9m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 701 resolved cases by this examiner. Grant probability derived from career allowance rate.

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