DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 10 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xia et al. (U.S. publication No. 2009/0093100).
Regarding claim 1, Xia teaches an integrated chip comprising:
a first conductive wire (Fig. 1F, left wire 109) over a substrate (101);
a second conductive wire (middle wire 105) over the substrate and laterally spaced from the first conductive wire (Fig. 1F);
a dielectric cap (111) laterally between the first conductive wire and the second conductive wire (Fig. 1F); and
a capping layer (115) over the second conductive wire and extending toward the first conductive wire beyond a sidewall of the second conductive wire (Fig. 1F).
Regarding claim 2, Xia teaches the integrated chip of claim 1, further comprising:
an etch stop layer (layer 104) between the first conductive wire and the second conductive wire and spaced below the dielectric cap.
Regarding claim 3, Xia teaches the integrated chip of claim 2, wherein the etch stop layer is on a sidewall of the first conductive wire and on the sidewall of the second conductive wire (see Fig. 1F, on a portion of the sidewalls at the bottom).
Regarding claim 4, Xia teaches the integrated chip of claim 3, wherein the capping layer is directly over the second conductive wire and the etch stop layer (Fig. 1F).
Regarding claim 5, Xia teaches the integrated chip of claim 2, wherein a lower surface of the dielectric cap, an upper surface of the etch stop layer, and a conductive sidewall of the first conductive wire partially delimit a cavity that is between the first conductive wire and the second conductive wire (Fig. 1F, cavity 114).
Regarding claim 6, Xia teaches the integrated chip of claim 1, wherein a sidewall of the capping layer is laterally offset from the sidewall of the second conductive wire in the direction of the first conductive wire (Fig. 1F).
Regarding claim 7, Xia teaches the integrated chip of claim 1, further comprising:
a dielectric layer (107) under the capping layer and between a sidewall of the dielectric cap and the sidewall of the second conductive wire (Fig. 1F).
Regarding claim 10, Xia teaches an integrated chip comprising:
a first conductive wire (Fig. 1F, left wire 109) over a substrate (101);
a second conductive wire (middle wire 109) over the substrate and laterally spaced from the first conductive wire (Fig. 1F);
a dielectric cap (111) over a cavity (114) and laterally between a sidewall of the first conductive wire and a sidewall of the second conductive wire (Fig. 1F); and
a dielectric layer (107) between the sidewall of the second conductive wire and a sidewall of the dielectric cap.
Regarding claim 13, Xia teaches the integrated chip of claim 10, further comprising:
an etch stop layer (etch stop 104) under the cavity, under the dielectric layer, and laterally between the sidewall of the first conductive wire and the sidewall of the second conductive wire (Fig. 1F).
Regarding claim 14, Xia teaches the integrated chip of claim 13, wherein the dielectric layer extends from a top of the second conductive wire and a top of the dielectric cap to a top of the etch stop layer (Fig. 1F).
Allowable Subject Matter
Claims 8-9 and 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 8, the prior art, alone or in combination, fails to teach or suggest a conductive sidewall of the first conductive wire partially delimit a cavity that is between the first conductive wire and the second conductive wire.
Regarding claims 9, the prior art, alone or in combination, fails to teach wherein the dielectric layer separates the dielectric cap from the second conductive wire, and wherein the dielectric cap is on a sidewall of the first conductive wire.
Regarding claims 11-12, the prior art, alone or in combination, fails to teach or suggest wherein the dielectric cap extends from the sidewall of the first conductive wire to a sidewall of the dielectric layer, and wherein the dielectric layer extends from the sidewall of the dielectric cap to the sidewall of the second conductive wire.
Regarding claims 15-20, the prior art, alone or in combination, fails to teach or suggest a first conductive wire over the first conductive via and extending beyond a sidewall of the first conductive via to over the first dielectric cap.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899
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