DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lembeye et al ( Lembeye, US 2017/0117239 A1 of IDS record).
Regarding claim 1, Lembeye shows a process for implementing a device, comprising, providing a metal submount (metal flange 206 in FIG. 3 and [0036]); arranging a first transistor die (transistor 220 in FIG. 3 and [0041]) on said metal submount; arranging a second transistor die (transistor 220) on said metal submount ( metal flange 206); providing a set of primary interconnects ( interconnect 234); and providing a set of secondary interconnects (interconnect 350), wherein the set of primary interconnects and the set of secondary interconnects are configured to provide RF signal ([0022]) coupling between the first transistor die and the second transistor die (transistor 220) by electromagnetic coupling underlined limitation considered function of the device).
Regarding claim 2, Lembeye shows a process for implementing a device, further comprising configuring the set of primary interconnects ( interconnect 234) and the set of secondary interconnects (interconnect 350) to provide an interstage match (see FIG. 3).
Regarding claim 3, Lembeye shows a process for implementing a device, comprising, wherein the set of primary interconnects ( interconnect 234) and the set of secondary interconnects (interconnect 350) comprise wires (see FIG. 3).
Regarding claim 4, Lembeye shows a process for implementing a device, comprising wherein the set of primary interconnects and the set of secondary interconnects comprise bond wires; and the process further comprising: implementing the set of primary interconnects and the set of secondary interconnects to provide a desired impedance based on a respective number of the bond wires, a respective size of the bond wires, a respective width of the bond wires, and/or a respective diameter of the bond wires ( wire 234, 350 and [0002]).
Regarding claim 5, Lembeye shows a process for implementing a device, comprising configuring the set of primary interconnects ( interconnect 234) and the set of secondary interconnects (interconnect 350) as a DC block between the first transistor die and the second transistor die (see FIG. 3).
Regarding claim 6, Lembeye shows a process for implementing a device, comprising attenuating and/or filtering lower frequency signals ( [0020]) transferred between the first transistor die and the second transistor die with the set of primary interconnects (interconnect 234) and the set of secondary interconnects (interconnect 350).
Regarding claim 7, Lembeye shows a process for implementing a device, comprising, wherein the first transistor die is implemented as a driver stage transistor ( transistor 220); and wherein the second transistor die is implemented as a final stage transistor (transistor 220).
Regarding claim 8, Lembeye shows a process for implementing a device, comprising configuring the set of primary interconnects (interconnect 234) and the set of secondary interconnects (interconnect 350) as a transformer to provide RF signal coupling between the first transistor die and the second transistor die (transistor 220).
Regarding claim 9, Lembeye shows a process for implementing a device, comprising configuring the set of primary interconnects (interconnect 234) and the set of secondary interconnects (interconnect 350) to fanout between the first transistor die and the second transistor die (transistor 220).
Regarding claim 10, Lembeye shows a process for implementing a device, comprising providing a first Integrated Passive Device (IPD) and a second Integrated Passive Device (IPD) (IPD 240), wherein the first transistor die connects to the first Integrated Passive Device (IPD) with one or more interconnects; and wherein the second transistor die connects to the second Integrated Passive Device (IPD) with one or more interconnects (see FIG. 3 with respect to FIG. 4).
Regarding claim 11, Lembeye shows a process for implementing a device, comprising connecting the first Integrated Passive Device (IPD) to the second Integrated Passive Device (IPD) (IPD 240) with the set of secondary interconnects; and connecting the first Integrated Passive Device (IPD) to the second Integrated Passive Device (IPD) with the set of primary interconnects (interconnect 234/350).
Regarding claim 12, Lembeye shows a process for implementing a device, comprising configuring the first Integrated Passive Device (IPD) with an inter-digitated array of one or more interconnect pads; and configuring the second Integrated Passive Device (IPD) (IPD 240)with an inter-digitated array of one or more interconnect pads (pad 244).
Regarding claim 13, Lembeye shows a process for implementing a device, comprising configuring the first Integrated Passive Device (IPD) with an inter-digitated array of capacitors; and configuring the second Integrated Passive Device (IPD) with an inter-digitated array capacitors ([0027]).
Regarding claim 14, Lembeye shows a process for implementing a device, comprising configuring the first Integrated Passive Device (IPD) with at least one capacitor; and configuring the second Integrated Passive Device (IPD) with at least one capacitor ([0027]).
Regarding claim 15, Lembeye shows a process for implementing a device, comprising, wherein the first Integrated Passive Device (IPD), the second Integrated Passive Device (IPD) ( IPD 240), the set of primary interconnects, and the set of secondary interconnects are configured to provide the RF signal from the first transistor die to the second transistor die (transistors 220).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893
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