DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 16-17 are objected to because of the following informalities:
In claim 16, line 2, the recitation of “ALD” should be changed to “Atomic Layer Deposition (ALD), for clarity.
In claim 17, line 1, the recitation of “the a” should be change to “a”, for clarity.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 and 4 of U.S. Patent No. 12,125,911. Although the claims at issue are not identical, they are not patentably distinct from each other because.
Instant Application 18/775,341
Claim
U.S. Patent No. 12,125,911
Claim
1
1, 2
2
4
3
1, 2
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7, 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0079054).
Regarding claim 1, Chen et al. discloses, as shown in Figure 8, a method comprising:
forming a first silicon nitride layer on a semiconductor substrate using Atomic Layer Deposition (ALD), wherein the forming the first silicon nitride layer comprises forming plurality of sub-layers (Figure 8, step 810, 820, 830);
performing a plurality of hydrogen treatments on the first silicon nitride layer, wherein each of the plurality of hydrogen treatments is performed after one of the plurality of sub-layers is formed (Figure 8, step 820); (it is noted that that Chen et al. discloses the repetition (step 830 of Figure 8) of different ALD cycles, [0166]). Chen et al. does not disclose forming a second silicon nitride layer extending on a semiconductor region using ALD, wherein the semiconductor regio is over the semiconductor substrate, and wherein the forming the second silicon nitride layer is free from hydrogen treatments. However, Chen et al. discloses the use of ALD cycles which do not use hydrogen and their benefit of densification and use of increased plasma power. Note Figures 2, 4, [0017]-[0019], [0037]-[0039], and [0134]-[0141]. Chen et al. further discloses that hydrogen containing cycles facilitate surface reactions and conformal deposition [0293], but also controlling the percentage of hydrogen in the SiN layer [0034]. Chen et al. does not disclose the forming of SiN layers in sequence. However, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the SiN layers in sequence as claimed by using ALD cycles with and without hydrogen, in order to have the desired densification and conformal, and to have the desired properties and composition.
Regarding claim 2, Chen et al. discloses the method further comprising:
generating hydrogen radicals using a process gas, wherein the process gas is free from silicon and nitrogen; and
removing ions generated from the process gas, wherein the hydrogen radicals are kept after the removing, and wherein the plurality of hydrogen treatments are performed using the hydrogen radicals [0017]-[0019], [0037]-[0039], and [0134]-[0141].
Regarding claim 3, Chen et al. discloses the first silicon nitride layer comprises a plurality of atomic layers formed atomic-layer-by-atomic-layer, and the plurality of hydrogen treatments comprise a treatment performed for each of the plurality of atomic layers (Figure 8, step 820).
Regarding claim 7, Chen et al. discloses the method further comprising performing a plurality of bombardment processes on the first silicon nitride layer using nitrogen, wherein each of the plurality of bombardment process is performed after one of the plurality of sub-layers is formed (Figure 8, step 830, [0280],[0293]-[0294], [0296]-[0297], [0301], [0303], and [0306]).
Regarding claim 16, Chen et al. discloses, as shown in Figure 8, a method comprising:
forming a first silicon nitride atomic layer through Atomic Layer Deposition (ALD) cycle comprising:
introducing a silicon-containing precursor into a process chamber and purging the silicon-containing precursor (Figure 8, step 810);
introducing hydrogen radicals into the process chamber and purging the hydrogen radicals (Figure 8, step 820);
introducing a nitrogen-containing precursor into the process chamber and purging the nitrogen-containing precursor (Figure 8, step 820); (it is noted that that Chen et al. discloses the repetition (step 830 of Figure 8) of different ALD cycles, [0166]). Chen et al. does not disclose forming a second silicon nitride atomic layer over the first silicon nitride atomic layer, the second silicon nitride atomic layer being formed through a second ALD cycle comprising: introducing the silicon-containing precursor into the process chamber; and introducing the nitrogen-containing precursor into the process chamber and purging the nitrogen-containing precursor, wherein the second ALD cycle is performed free from hydrogen radicals introducing and purging processes. However, Chen et al. discloses the use of ALD cycles which do not use hydrogen and their benefit of densification and use of increased plasma power. Note Figures 2, 4, [0017]-[0019], [0037]-[0039], and [0134]-[0141]. Chen et al. further discloses that hydrogen containing cycles facilitate surface reactions and conformal deposition [0293], but also controlling the percentage of hydrogen in the SiN layer [0034]. Chen et al. does not disclose the forming of SiN layers in sequence. However, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the SiN layers in sequence as claimed by using ALD cycles with and without hydrogen, in order to have the desired densification and conformal, and to have the desired properties and composition.
Regarding claim 17, Chen et al. discloses a first one of the first ALD cycle and the second ALD cycle comprises a bombardment process on a respective one of the first silicon nitride atomic layer and the second silicon nitride atomic layer, and wherein the bombardment process is performed using argon or nitrogen [0280],[0293]-[0294], [0296]-[0297], [0301], [0303], and [0306].
Regarding claim 18, Chen et al. discloses the bombardment process is performed using argon [0280],[0293]-[0294], [0296]-[0297], [0301], [0303], and [0306].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0079054) in view of Chang et al. (US 2016/0351568)
Chen et al. discloses the claimed invention including the method as explained in the above rejection. Chen et al. does not disclose etching a gate stack to form an opening in the gate stack, wherein parts of the first silicon nitride atomic layer and the second silicon nitride atomic layer are filled into the opening. However, Chang et al. discloses a method comprising etching a gate stack to form an opening in the gate stack, wherein parts of the first silicon nitride atomic layer and the second silicon nitride atomic layer are filled into the opening. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to perform the method of Chen et al. comprising etching a gate stack to form an opening in the gate stack, such as taught by Chang et al. in order to form the desired configuration for the device.
Allowable Subject Matter
Claims 4-6 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8-15 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant' s claims 4-6, 8-15, and 19 are allowable over the references of record because none of these references disclose or can be combined to yield the claimed method comprising the first silicon nitride layer forms a dielectric isolation region separating a semiconductor fin into a first portion and a second portion, and wherein the second silicon nitride layer is used for generating a dislocation plane in the semiconductor region, as recited in claim 4; none of these references disclose or can be combined to yield the method comprising the first silicon nitride layer forms a dielectric isolation region separating a gate stack into a first portion and a second portion, and wherein the second silicon nitride layer is used for generating a dislocation plane in the semiconductor region, as recited in claim 5; none of these references disclose or can be combined to yield the method comprising forming a gate stack over a semiconductor region, forming a first silicon nitride layer separating the gate stack into a first portion and a second portion, wherein the forming the first silicon nitride layer comprises a first plurality of Atomic Layer Deposition (ALD) cycles, each comprising: a first process for conducting a silicon-containing precursor, a second process for conducting hydrogen radicals, and a third process for conducting a nitrogen-containing precursor, performing a plurality of bombardment processes on the first silicon nitride layer, wherein each of the plurality of bombardment processes is performed after a sub-layer of the first silicon nitride layer is formed, and the second silicon nitride layer comprises a second plurality of ALD cycles, each comprising: a fourth process for conducting the silicon-containing precursor, and a fifth process for conducting the nitrogen-containing precursor, wherein the second plurality of ALD cycles are free from processes for introducing hydrogen radicals, in combination with the remaining claimed limitations of claim 8; none of these references disclose or can be combined to yield the method comprising a second one of the first ALD cycle and the second ALD cycle is free from bombardment processes, as recited in claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JACOB CHOI can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUNG K VU/ Primary Examiner, Art Unit 2897