DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Cross-Reference to Related Applications
2. This application claims benefit of 63/567,854 03/20/2024.
Oath/Declaration
3. The oath/declaration filed on 08/22/2024 is acceptable.
Information Disclosure Statement
4. The office acknowledges receipt of the following items from the applicant:
Information Disclosure Statement (IDS) filed on 07/17/2024.
Specification
5. The specification is objected to for the following reason: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP 606.01).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. Claims 1 and 9 are rejected under 35 U.S.C. 103(a) as being unpatentable over Wu et al., hereafter “Wu” (U.S. Publication No. 2024/0107736 A1) in view of Jung et al., hereafter “Jung” (U.S. Publication No. 2024/0088150 A1).
Regarding claim 1, Wu discloses a semiconductor device structure, comprising:
a substrate (12);
an insulating material (14a, para [0032]) disposed on the substrate (12);
a first fin structure (Left 106) extending upwardly from the substrate (12) through the insulating material (14a);
a second fin structure (Right 106) extending upwardly from the substrate (12) through the insulating material (14a), the first (Left 106) and second fin structures (Right 106) extending along a first direction; (X-direction, para [0031]);
a first isolation trench structure (125, para [0050]) disposed between the first (1st 106) and second fin structures (2nd 106), the first isolation trench structure (125) extending through the insulating material (14a) along a second direction (the gate isolation structure 125 extends through the gate structure 114 and the STI feature 14a, and extends into the p well 111, para [0050] refers extending along Z-direction as orientation in direction) perpendicular to the first direction (X-direction) (Fig. 11 and para [0046]-[0050]).
Wu discloses the features of the claimed invention as discussed above, but does not disclose the first isolation trench structure comprising: a first portion extending a first depth into the substrate; and a second portion extending a second depth into the substrate, wherein the second depth is different than first depth.
Jung, however, discloses the first isolation trench structure (190) comprising: a first portion (194) extending a first depth into the substrate (102); and a second portion (198) extending a second depth into the substrate (102), wherein the second depth is different than first depth (Fig. 2A-2B and para [0052]-[0058]).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Wu to provide the first isolation trench structure comprising: a first portion extending a first depth into the substrate; and a second portion extending a second depth into the substrate, wherein the second depth is different than first depth as taught by Jung for a purpose of improving the integral performance and reliability of the semiconductor device structure.
Regarding claim 9, Wu and Jung (citations to Wu unless otherwise noted) disclose wherein each of the first and second portions of the first isolation trench structure has a curved profile (Figs. 2A-2B).
Allowable Subject Matter
7. The following is a statement of reason for the indication of allowable subject matter:
Regarding claim 10, Wu et al. (U.S. Publication No. 2024/0107736 A1) discloses a semiconductor device structure, comprising: a substrate (12); a first fin structure (Left 106) extending upwardly from the substrate (12); a second fin structure (Right 106) extending upwardly from the substrate (12), the first (Left 106) and second fin structures (Right 106) being parallelly arranged along a first direction (Z-direction); a first isolation trench structure (125) disposed between the first (left 106) and second fin structures (Right 106) (Fig. 11 and para [0046]-[0050]).
Jung et al. (U.S. Publication No. 2024/0088150 A1) discloses the first isolation trench structure (190) extending along a second direction (the fin isolation insulator 190 may extend lengthwise in a second horizontal direction (Y direction) between the plurality of pairs of fin-type active regions FA) perpendicular to the first direction (Z-direction) (Figs. 2A-2B and para [0024]).
Wu and Jung, however, either alone or together in any combination, do not disclose, teach, or otherwise suggest a feature of “a second isolation trench structure disposed between the first and second fin structures, the second isolation trench structure extending along the second direction; and a third isolation trench structure disposed between the first and second fin structures, the third isolation trench extending along the first direction to across a portion of the first isolation trench structure, and the third isolation trench structure being separated from the second isolation trench structure by an interlayer dielectric (ILD) layer” as cited in the independent claim 10.
Claims 11-16 are directly or indirectly depend on the independent claim 10, then, they are also being allowed.
Regarding claim 17, Wu et al. (U.S. Publication No. 2024/0107736 A1) discloses a method for forming a semiconductor device structure, comprising: forming a plurality of fin structures (106/108) from a substrate (12), each fin structure (106/108) extending along a first direction (X-direction, para [0031]); forming an insulating material (14a) on the substrate (12); and forming a gate electrode layer (114) over the insulating material (14a) (Figs. 2A-2B).
CHANG et al. (U.S. Publication No. 2023/0064705 A1) discloses each fin structure (202) comprising a plurality of semiconductor layers (106b/106c/106d) vertically stacked; and the gate electrode layer (3302) surrounding a portion of each semiconductor layer (106b/106c/106d) (Figs. 2 and 33 and para [0038] and [0087]).
Wu and CHANG, however, either alone or together in any combination, do not disclose, teach, or otherwise suggest a feature of “removing portions of the gate electrode layer and the insulating material to form a first isolation trench, the first isolation trench extending along the first direction; filling the first isolation trench with a first dielectric material to form a first isolation trench structure; removing portions of the gate electrode layer, the semiconductor layers of one or more fin structures of the plurality of fin structures, the first isolation trench structure, the insulating material, and the substrate to form a second isolation trench extending along a second direction perpendicular to the first direction; and filling the second isolation trench with a second dielectric material to form a second isolation trench structure” as cited in the independent claim 17.
Claims 18-20 are directly or indirectly depend on the independent claim 17, then, they are also being allowed.
Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Arts
8. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
More (U.S. Publication No. 2023/0119286 A1) discloses substate isolation feature 40 is disposed over substrate 20, along sidewalls of the recessed portions of fin 15, and along sidewalls of lower portions of the non-recessed portion of fin 15. Gate stack 25 extends over the top of substrate isolation feature 40. In some embodiments, substrate isolation feature 40 surrounds a lower portion of fin 15. In some embodiments, fin 15 is not recessed in the source/drain regions of the FinFET, and epitaxial source/drains 30 wrap fin 15 (e.g., epitaxial source/drains 30 are disposed on tops and opposing sidewalls of fin 15 (Fig. 1 and para [0012]).
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHUC T DANG/Primary Examiner, Art Unit 2897
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