DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1, 4, 6, 8 & 15-17 of U.S. Patent No. 11742218, in view of Shah (US PG Pub. No. 2022/0199429, hereinafter Shah).
Regarding claim 1, claim(s) 1, 4, 6 of US Patent 11742218 recited “A method for forming a semiconductor device package, comprising: bonding a semiconductor device to a first surface of a package substrate; placing a metal lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the metal lid and a top surface of the semiconductor device; heating the metal TIM to melt the metal TIM; pressing the metal lid downward so that the molten metal TIM laterally flows toward a boundary of the semiconductor device along a first direction, and an outermost point of a lateral sidewall of the molten metal TIM extends beyond the boundary of the semiconductor device; lifting the metal lid upward so that the molten metal TIM laterally flows toward a center of the top surface of the semiconductor device along a second direction opposite to the first direction, and the outermost point of the lateral sidewall of the molten metal TIM is within the boundary of the semiconductor device; and bonding the metal lid to the semiconductor device through the metal TIM by cooling the molten metal TIM; wherein after lifting the metal lid, the outermost point of the lateral sidewall of the molten metal TIM is aligned with the boundary of the semiconductor device, or closer to the center of the top surface of the semiconductor device than the boundary of the semiconductor device in a lateral direction; wherein after lifting the metal lid, a shape of the lateral sidewall of the molten metal TIM in a longitudinal section is a concave arc.
US Patent 11742218 does not recite pressing the metal lid downward so that the molten metal TIM laterally flows beyond a boundary of the semiconductor device,
Shah discloses in Fig 3B the TIM (202) beyond a boundary of the semiconductor device(302a),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Shah to the teachings of US Patent 11742218 in order to minimize reducing the efficacy of thermal transfer between the chip module and the lid [0001, Shah]. In doing so, pressing the metal lid downward so that the molten metal[US Patent 11742218] TIM (202) laterally flows beyond a boundary of the semiconductor device(302a),
Re claim 2 US Patent 11742218 and Shah disclose the method as claimed in claim 1, wherein the metal lid is pressed down using a thermal compression bonding head, and the metal lid is lifted up using the thermal compression bonding head[US Patent 11742218].
Re claim 3 US Patent 11742218 and Shah disclose the method as claimed in claim 1, wherein after pressing the metal lid and before lifting the metal lid, the molten metal TIM (202 OF SHAH) has a first thickness in a vertical direction, and wherein after lifting the metal lid, the molten metal TIM (202 OF SHAH) has a second thickness in the vertical direction, the second thickness being greater than the first thickness.
Re claim 4 US Patent 11742218 and Shah disclose the method as claimed in claim 1, wherein after lifting the metal lid, an outermost point of the lateral sidewall of the molten metal TIM (202 OF SHAH) is aligned with the boundary of the semiconductor device in a lateral direction.
Re claim 5 US Patent 11742218 and Shah disclose the method as claimed in claim 1, wherein after lifting the metal lid, an outermost point of the lateral sidewall of the molten metal TIM (202 OF SHAH) is closer to a center of the top surface of the semiconductor device than the boundary of the semiconductor device in a lateral direction.
Re claim 6 US Patent 11742218 and Shah disclose the method as claimed in claim 1, further comprising forming a buffer layer on the top surface of the semiconductor device before the metal TIM (202 OF SHAH) is provided over the top surface of the semiconductor device.
Re claim 7 US Patent 11742218 and Shah disclose the method as claimed in claim 1, further comprising coating the metal TIM (202 OF SHAH) with a flux layer before the metal TIM (202 OF SHAH) is provided between the metal lid and the top surface of the semiconductor device.
Re claim 8 US Patent 11742218 and Shah disclose the method as claimed in claim 7, wherein after the metal lid is bonded to the semiconductor device through the metal TIM (202 OF SHAH), a gap is formed between a bottom surface of the metal lid and the first surface of the package substrate, and the method further comprises: providing a cleaning fluid into a space between the metal lid and the package substrate through the gap to remove a flux residue[US Patent 11742218].
Re claim 9 US Patent 11742218 and Shah disclose the method as claimed in claim 8, further comprising: applying adhesive to the gap between the bottom surface of the metal lid and the first surface of the package substrate, after the removal of the flux residue[US Patent 11742218].
Re claim 10 US Patent 11742218 and Shah disclose the method as claimed in claim 1, further comprising: providing an adhesive layer between a bottom surface of the metal lid and the first surface of the package substrate[US Patent 11742218].
Re claim 11 US Patent 11742218 and Shah disclose the method as claimed in claim 1, wherein the metal TIM (202 OF SHAH) is a solder-based TIM (202 OF SHAH).
Regarding claim 12, claim(s) 1 & 8 of US Patent 11742218 recited “A method for forming a semiconductor device package, comprising: bonding a semiconductor device to a first surface of a package substrate; placing a metal lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the metal lid and a top surface of the semiconductor device; heating the metal TIM to melt the metal TIM; pressing the metal lid downward so that the molten metal TIM laterally flows toward a boundary of the semiconductor device along a first direction, and an outermost point of a lateral sidewall of the molten metal TIM extends beyond the boundary of the semiconductor device; lifting the metal lid upward so that the molten metal TIM laterally flows toward a center of the top surface of the semiconductor device along a second direction opposite to the first direction, and the outermost point of the lateral sidewall of the molten metal TIM is within the boundary of the semiconductor device; and bonding the metal lid to the semiconductor device through the metal TIM by cooling the molten metal TIM; further comprising coating the metal TIM with a flux layer before the metal TIM is provided between the metal lid and the top surface of the semiconductor device.
US Patent 11742218 does not recite pressing the metal lid downward so that the molten TIM laterally flows beyond a boundary of the semiconductor device;
Shah discloses in Fig 3B the TIM (202) beyond a boundary of the semiconductor device(302a),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Shah to the teachings of US Patent 11742218 in order to minimize reducing the efficacy of thermal transfer between the chip module and the lid [0001, Shah]. In doing so, pressing the metal lid downward so that the molten metal[US Patent 11742218] TIM (202 of Shah) laterally flows beyond a boundary of the semiconductor device(302a),
Re claim 13 US Patent 11742218 and Shah disclose the method as claimed in claim 12, wherein after lifting the metal lid, the outermost point of the lateral sidewall of the molten TIM (202 OF SHAH) is aligned with the boundary of the semiconductor device, or closer to a center of the top surface of the semiconductor device than the boundary of the semiconductor device in a lateral direction.
Re claim 14 US Patent 11742218 and Shah disclose the method as claimed in claim 13, wherein after lifting the metal lid, a shape of the lateral sidewall of the molten TIM (202 OF SHAH) in a longitudinal section is a concave arc.
Re claim 15 US Patent 11742218 and Shah disclose the method as claimed in claim 13, wherein after lifting the metal lid, a shape of the lateral sidewall of the molten TIM (202 OF SHAH) in a longitudinal section is a straight.
Re claim 16 US Patent 11742218 and Shah disclose the method as claimed in claim 12, wherein after the metal lid is bonded to the semiconductor device through the TIM (202 OF SHAH), a gap is formed between a bottom surface of the metal lid and the first surface of the package substrate, and the method further comprises: providing a cleaning fluid into a space between the metal lid and the package substrate through the gap to remove a flux residue[US Patent 11742218].
Re claim 17 US Patent 11742218 and Shah disclose the method as claimed in claim 16, further comprising: applying adhesive to the gap between the bottom surface of the metal lid and the first surface of the package substrate, after the removal of the flux residue[US Patent 11742218].
Re claim 18 US Patent 11742218 and Shah disclose the method as claimed in claim 12, wherein the metal lid is pressed down using a thermal compression bonding head, and the metal lid is lifted up using the thermal compression bonding head, wherein during processes of pressing and lifting the metal lid, the thermal compression bonding head continues to contact the metal lid[US Patent 11742218].
Re claim 19 US Patent 11742218 and Shah disclose the method as claimed in claim 12, wherein the heating of the TIM (202 OF SHAH), the pressing of the metal lid, the lifting of the metal lid, and the bonding of the metal lid are performed in a same chamber.
Regarding claim 20, claim(s) 15, 16 & 17 of US Patent 11742218 recited “A method for forming a semiconductor device package, comprising: bonding a semiconductor device to a first surface of a package substrate; placing a metal lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the metal lid and a top surface of the semiconductor device; heating the metal TIM to melt the metal TIM; pressing the metal lid downward so that the molten metal TIM laterally flows toward a boundary of the semiconductor device, and an outermost point of a lateral sidewall of the molten metal TIM extends beyond the boundary of the semiconductor device; lifting the metal lid upward so that the molten metal TIM laterally flows back, and an outermost point of the lateral sidewall of the molten metal TIM is within the boundary of the semiconductor device; and bonding the metal lid to the semiconductor device through the metal TIM by cooling the molten metal TIM, wherein after the metal lid is bonded to the semiconductor device through the metal TIM, a gap is formed between a bottom surface of the metal lid and the first surface of the package substrate, the gap extends from an inner wall of the metal lid to an outer wall of the metal lid, and no adhesive is provided in the gap; wherein after lifting the metal lid, the outermost point of the lateral sidewall of the molten metal TIM is aligned with the boundary of the semiconductor device, or closer to a center of the top surface of the semiconductor device than the boundary of the semiconductor device in a lateral direction; wherein after lifting the metal lid, a shape of the lateral sidewall of the molten metal TIM in a longitudinal section is a concave arc, and the lateral sidewall of the molten metal TIM comprises two end points and an intermediate point between the two end points, wherein the two end points are connected to the metal lid and the semiconductor device, respectively, and closer to the boundary of the semiconductor device than the intermediate point in a lateral direction.
US Patent 11742218 does not recite pressing the metal lid downward so that the molten TIM laterally flows beyond a boundary of the semiconductor device;
Shah discloses in Fig 3B the TIM (202) beyond a boundary of the semiconductor device(302a),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Shah to the teachings of US Patent 11742218 in order to minimize reducing the efficacy of thermal transfer between the chip module and the lid [0001, Shah]. In doing so, pressing the metal lid downward so that the molten metal[US Patent 11742218] TIM (202) laterally flows beyond a boundary of the semiconductor device(302a),
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Prosecution Insights