DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Statutory Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-3 are rejected under 35 U.S.C. 101 as claiming the same invention as that of Claim 3 of prior U.S. Patent No. US 12068398 B2, hereinafter Pat. No. ‘398. This is a statutory double patenting rejection.
Regarding Claim 1,
Pat. No. ‘398 recites:
A method for making a semiconductor device, comprising:
forming a first gate stack over a first fin;
(Claim 1: Lin. 10 – 15)
forming a first gate spacer extending along a side of the first gate stack, the first gate spacer comprising a first dielectric material;
(Claim 1: Lin. 10 – 15)
forming a second gate spacer over the first gate spacer, the second gate spacer comprising silicon germanium;
(Claim 1: Lin. 15 – 20)
forming a third gate spacer over the second gate spacer, the third gate spacer comprising a second dielectric material;
(Claim 1: Lin. 20 – 25)
forming a source/drain region adjacent the third gate spacer;
(Claim 1: Lin. 20 – 25)
depositing an interlayer dielectric (ILD) over the source/drain region, the ILD comprising a third dielectric material; and
(Claim 1: Lin. 20 – 25)
removing at least a portion of the second gate spacer to form a void, while exposing a top surface of the ILD,
(Claim 1: Lin. 25 – 30)
wherein the void includes a vertical portion extending between the first gate spacer and the source/drain region, and between the first gate spacer and the ILD, and
(Claim 2: Lin. 30 – 35)
wherein the void includes a horizontal portion extending beneath the source/drain region.
(Claim 3: Lin. 35 – 40)
Regarding Claim 3,
Pat. No. ‘398 recites:
The method of claim 1, wherein the step of removing at least a portion of the second gate spacer leaves the first gate spacer, the third gate spacer, and the ILD intact.
(Claim 1: Lin. 25)
Nonstatutory Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3, & 15 – 18 are rejected on the ground of nonstatutory double patenting as being anticipated by Independent Claim 1 and its dependents of Pat. No. ‘398.
Regarding Claim 1,
Pat. No. ‘398 recites:
A method for making a semiconductor device, comprising:
forming a first gate stack over a first fin;
(Claim 1: Lin. 10 – 15)
forming a first gate spacer extending along a side of the first gate stack, the first gate spacer comprising a first dielectric material;
(Claim 1: Lin. 10 – 15)
forming a second gate spacer over the first gate spacer, the second gate spacer comprising silicon germanium;
(Claim 1: Lin. 15 – 20)
forming a third gate spacer over the second gate spacer, the third gate spacer comprising a second dielectric material;
(Claim 1: Lin. 20 – 25)
forming a source/drain region adjacent the third gate spacer;
(Claim 1: Lin. 20 – 25)
depositing an interlayer dielectric (ILD) over the source/drain region, the ILD comprising a third dielectric material; and
(Claim 1: Lin. 20 – 25)
removing at least a portion of the second gate spacer to form a void, while exposing a top surface of the ILD,
(Claim 1: Lin. 25 – 30)
wherein the void includes a vertical portion extending between the first gate spacer and the source/drain region, and between the first gate spacer and the ILD, and
(Claim 2: Lin. 30 – 35)
wherein the void includes a horizontal portion extending beneath the source/drain region.
(Claim 3: Lin. 35 – 40)
Regarding Claim 3,
Pat. No. ‘398 recites:
The method of claim 1, wherein the step of removing at least a portion of the second gate spacer leaves the first gate spacer, the third gate spacer, and the ILD intact.
(Claim 1: Lin. 25)
Regarding Claim 15,
Pat. No. ‘398 recites:
A method for making a semiconductor device, comprising:
forming a first gate stack over a first fin;
(Claim 1: Lin. 10 – 15)
forming a first gate spacer extending along a side of the first gate stack, the first gate spacer comprising a first dielectric material;
(Claim 1: Lin. 15)
forming a second gate spacer over the first gate spacer, the second gate spacer comprising silicon germanium;
(Claim 1: Lin. 15 – 20)
forming a third gate spacer over the second gate spacer, the third gate spacer comprising a second dielectric material;
(Claim 1: Lin. 20)
forming a source/drain region adjacent the third gate spacer;
(Claim 1: Lin. 20 – 25)
depositing an interlayer dielectric (ILD) over the source/drain region, the ILD comprising a third dielectric material; and
(Claim 1: Lin. 25)
removing at least a portion of the second gate spacer to form a void, while exposing a top surface of the ILD,
(Claim 1: Lin. 25 – 30)
wherein the first gate stack is formed over a second fin in parallel with the first fin.
(Claim 6: Lin. 50)
Regarding Claim 16,
Pat. No. ‘398 recites:
The method of claim 15, wherein the source/drain region is also formed in the second fin.
(Claim 6: Lin. 50)
Regarding Claim 17,
Pat. No. ‘398 recites:
The method of claim 15, wherein the void further extends beneath the source/drain region.
(Claim 6: Lin. 50 – 55)
Regarding Claim 18,
Pat. No. ‘398 recites:
The method of claim 15, wherein the step of removing at least a portion of the second gate spacer leaves the first gate spacer, the third gate spacer, and the ILD intact.
(Claim 1: Lin. 30)
Claims 4 & 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Independent Claim 1 and its dependents of Pat. No. ‘398. Although the claims at issue are not identical, they are not patentably distinct from each other because of the reasoning provided below.
Regarding Claim 4,
Pat. No. ‘398 does not recite:
The method of claim 1, wherein the void includes air or a vacuum.
However, under a broadest reasonable interpretation, “air” may comprise any gas or gaseous mixture. Therefore, the void including any gas or gaseous mixture or vacuum would have been obvious to PHOSITA.
Regarding Claim 20,
Pat. No. ‘398 does not recite:
The method of claim 15, wherein the void includes air or a vacuum.
However, under a broadest reasonable interpretation, “air” may comprise any gas or gaseous mixture. Therefore, the void including any gas or gaseous mixture or vacuum would have been obvious to PHOSITA.
Claims 1 & 15 – 18 are rejected on the ground of nonstatutory double patenting as being anticipated by Independent Claim 10 and its dependents of Pat. No. ‘398.
Regarding Claim 1,
Pat. No. ‘398 recites:
A method for making a semiconductor device, comprising:
forming a first gate stack over a first fin;
(Claim 10: Lin. 65)
forming a first gate spacer extending along a side of the first gate stack, the first gate spacer comprising a first dielectric material;
(Claim 10: Lin. 65)
forming a second gate spacer over the first gate spacer, the second gate spacer comprising silicon germanium;
(Claim 10: Lin. 0)
forming a third gate spacer over the second gate spacer, the third gate spacer comprising a second dielectric material;
(Claim 10: Lin. 0 – 5)
forming a source/drain region adjacent the third gate spacer;
(Claim 10: Lin. 5 – 10)
depositing an interlayer dielectric (ILD) over the source/drain region, the ILD comprising a third dielectric material; and
(Claim 11: Lin. 15)
removing at least a portion of the second gate spacer to form a void,
(Claim 10: Lin. 10)
while exposing a top surface of the ILD,
(Claim 11: Lin. 15 – 20)
wherein the void includes a vertical portion extending between the first gate spacer and the source/drain region, and between the first gate spacer and the ILD, and
(Claim 14: Lin. 25 – 30)
wherein the void includes a horizontal portion extending beneath the source/drain region.
(Claim 15: Lin. 30)
Regarding Claim 15,
Pat. No. ‘398 recites:
A method for making a semiconductor device, comprising:
forming a first gate stack over a first fin;
(Claim 10: Lin. 60 – 65)
forming a first gate spacer extending along a side of the first gate stack, the first gate spacer comprising a first dielectric material;
(Claim 10: Lin. 65)
forming a second gate spacer over the first gate spacer, the second gate spacer comprising silicon germanium;
(Claim 10: Lin. 0)
forming a third gate spacer over the second gate spacer, the third gate spacer comprising a second dielectric material;
(Claim 10: Lin. 0 – 5)
forming a source/drain region adjacent the third gate spacer;
(Claim 10: Lin. 5 – 10)
depositing an interlayer dielectric (ILD) over the source/drain region, the ILD comprising a third dielectric material; and
(Claim 11: Lin. 15)
removing at least a portion of the second gate spacer to form a void,
(Claim 10: Lin. 10)
while exposing a top surface of the ILD,
(Claim 11: Lin. 15 – 20)
wherein the first gate stack is formed over a second fin in parallel with the first fin.
(Claim 10: Lin. 60 – 65)
Regarding Claim 16,
Pat. No. ‘398 recites:
The method of claim 15, wherein the source/drain region is also formed in the second fin.
(Claim 10: Lin. 5 – 10)
Regarding Claim 17,
Pat. No. ‘398 recites:
The method of claim 15, wherein the void further extends beneath the source/drain region.
(Claim 15: Lin. 30)
Regarding Claim 18,
Pat. No. ‘398 recites:
The method of claim 15, wherein the step of removing at least a portion of the second gate spacer leaves the first gate spacer, the third gate spacer, and the ILD intact.
(Claim 12: Lin. 20)
Claims 4 & 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Independent Claim 10 and its dependents of Pat. No. ‘398. Although the claims at issue are not identical, they are not patentably distinct from each other because of the reasoning provided below.
Regarding Claim 4,
Pat. No. ‘398 does not recite:
The method of claim 1, wherein the void includes air or a vacuum.
However, under a broadest reasonable interpretation, “air” may comprise any gas or gaseous mixture. Therefore, the void including any gas or gaseous mixture or vacuum would have been obvious to PHOSITA.
Regarding Claim 20,
Pat. No. ‘398 does not recite:
The method of claim 15, wherein the void includes air or a vacuum.
However, under a broadest reasonable interpretation, “air” may comprise any gas or gaseous mixture. Therefore, the void including any gas or gaseous mixture or vacuum would have been obvious to PHOSITA.
Claims 1, 15 – 17, & 20 are rejected on the ground of nonstatutory double patenting as being anticipated by Independent Claim 18 and its dependents of Pat. No. ‘398.
Regarding Claim 1,
Pat. No. ‘398 recites:
A method for making a semiconductor device, comprising:
forming a first gate stack over a first fin;
(Claim 18: Lin. 40 – 45)
forming a first gate spacer extending along a side of the first gate stack, the first gate spacer comprising a first dielectric material;
(Claim 18: Lin. 45 – 50)
Note, Pat. No. ‘398 appears to have a 112(b) issue, reciting “the dummy gate stack” without a proper antecedent basis. By the surrounding claim language, it is presumed Pat. No. ‘398 intended to recite “the first gate stack”, instead.
forming a second gate spacer over the first gate spacer, the second gate spacer comprising silicon germanium;
(Claim 18: Lin. 50)
forming a third gate spacer over the second gate spacer, the third gate spacer comprising a second dielectric material;
(Claim 18: Lin. 50 – 55)
forming a source/drain region adjacent the third gate spacer;
(Claim 18: Lin. 55)
depositing an interlayer dielectric (ILD) over the source/drain region, the ILD comprising a third dielectric material; and
(Claim 18: Lin. 60)
removing at least a portion of the second gate spacer to form a void,
(Claim 18: Lin. 60 – 65)
while exposing a top surface of the ILD,
(Claim 18: Lin. 60 – 65)
wherein the void includes a vertical portion extending between the first gate spacer and the source/drain region, and between the first gate spacer and the ILD, and
(Claim 19: Lin. 65)
wherein the void includes a horizontal portion extending beneath the source/drain region.
(Claim 19: Lin. 0 – 5)
Regarding Claim 15,
Pat. No. ‘398 recites:
A method for making a semiconductor device, comprising:
forming a first gate stack over a first fin;
(Claim 18: 40 – 45)
forming a first gate spacer extending along a side of the first gate stack, the first gate spacer comprising a first dielectric material;
(Claim 18: Lin. 45 – 50)
Note, Pat. No. ‘398 appears to have a 112(b) issue, reciting “the dummy gate stack” without a proper antecedent basis. By the surrounding claim language, it is presumed Pat. No. ‘398 intended to recite “the first gate stack”, instead.
forming a second gate spacer over the first gate spacer, the second gate spacer comprising silicon germanium;
(Claim 18: Lin. 50)
forming a third gate spacer over the second gate spacer, the third gate spacer comprising a second dielectric material;
(Claim 18: Lin. 50 – 55)
forming a source/drain region adjacent the third gate spacer;
(Claim 18: Lin. 55)
depositing an interlayer dielectric (ILD) over the source/drain region, the ILD comprising a third dielectric material; and
(Claim 18: Lin. 60)
removing at least a portion of the second gate spacer to form a void, while exposing a top surface of the ILD,
(Claim 18: Lin. 60 – 65)
wherein the first gate stack is formed over a second fin in parallel with the first fin.
(Claim 18: Lin. 40 – 45)
Regarding Claim 16,
Pat. No. ‘398 recites:
The method of claim 15, wherein the source/drain region is also formed in the second fin.
(Claim 18: Lin. 55)
Regarding Claim 17,
Pat. No. ‘398 recites:
The method of claim 15, wherein the void further extends beneath the source/drain region.
(Claim 19: Lin. 0 – 5)
Regarding Claim 20,
Pat. No. ‘398 recites:
The method of claim 15, wherein the void includes air or a vacuum.
(Claim 20: Lin. 5)
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over Independent Claim 18 and its dependents of Pat. No. ‘398. Although the claims at issue are not identical, they are not patentably distinct from each other because of the reasoning provided below.
Regarding Claim 4,
Pat. No. ‘398 does not recite:
The method of claim 1, wherein the void includes air or a vacuum.
However, under a broadest reasonable interpretation, “air” may comprise any gas or gaseous mixture. Therefore, the void including any gas or gaseous mixture or vacuum would have been obvious to PHOSITA.
Allowable Subject Matter
Claims 7 – 14 are allowed.
The following is the Examiner’s statement of reasons for allowance:
Regarding Claim 7,
The closest prior art of record YANG (US 20210020757 A1) discloses:
A method (Fig. 1A – 1B: 100) for making a semiconductor device (Fig. 2 – 16: 200), comprising:
forming a dummy gate stack (Fig. 2: 214-1) over a first fin (Fig. 2: 204-1) and a second fin (Fig. 2: 204-2);
forming (Par. 21) a first gate spacer (Fig. 3: 215) extending along a side of the dummy gate stack (214-1),
the first gate spacer (215) comprising a first dielectric material (Par. 22);
forming (Par. 21) a second gate spacer (Fig. 3: 216) over the first gate spacer (215),
the second gate spacer (216)…
forming (Par. 21) a third gate spacer (Fig. 3: 217) over the second gate spacer (216),
the third gate spacer (217) comprising a second dielectric material (Par. 22);
forming (Par. 21) a source/drain region (Fig. 3: 210/211) adjacent the [second] gate spacer (216);
depositing (Par. 19) an interlayer dielectric (ILD) (Fig. 6: 208/219) over the source/drain region (210/211),
the ILD comprising a third dielectric material (Par. 19);
removing (Fig. 7) at least a portion of the second gate spacer (216) to form a void (220), while exposing a top surface of the ILD (219 of 208/219);
depositing (Par. 26) a dielectric layer (Fig. 8-2: 221/222) over the void (220); and
removing (Fig. 9-2) portions of the dielectric layer (221 of 221/222) disposed outside of the void (220) with a planarization process (Par. 27),
causing remaining portions of the dielectric layer (222 of 221/222) forming dielectric plugs (Par. 26) to seal the void (220).
YANG does not disclose:
forming (Par. 21) a source/drain region (Fig. 3: 210/211) adjacent the third gate spacer (217);
The primary reason for the allowance of this claim is the inclusion of the limitation “forming a source/drain region adjacent the third gate spacer,” which is not found in the prior art of record. YANG, the closest prior art of record, teaches “forming a third gate spacer” and “forming a source/drain region,” but performs the formation of the source/drain region before the formation of the third gate spacer (YANG Par. 21) instead of after, as implicitly required by the grammatical structure of Applicant’s claim language. Although YANG teaches the individual operations, the evidence of record does not establish that a person having ordinary skill in the art would have had a reasonable expectation of success in rearranging the operations to the implicit claimed order to predictably preserve YANG’s disclosed fabrication process and resulting device. Therefore, a rational basis for rearranging YANG’s process steps to the implicit claimed order is not established. Accordingly, the limitation “forming a source/drain region adjacent the third gate spacer” is considered to define this claim patentably over the prior art of record.
Claims 8 – 14 are allowable by virtue of their dependency from Claim 7.
Any comments considered necessary by Applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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