DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Invention I, (claims 1-8 and 16-20), in the reply filed on
07/01/2026 is acknowledged. Claims 9-15 are canceled. Claims 21-27 are new. Claims 1-8 and 16-27 are pending.
Claims 1-8 and 16-20 and 22-26 corresponds to Species showed in Figure 4, but Claim 27 corresponds to another Species showed in Figure 9, claim 21 is a generic claim. For these reasons, claim 27 is withdrawn by consideration.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 25-26 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12074024 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 25 include the limitation “a third buried oxide layer disposed below the transistor, and vertically spaced from the first buried oxide layer and the second buried oxide layer”, and claim 26 depends of claim 25. Claim 1 (US 12074024B2) includes the limitation of “all of the plurality of first buried oxide layers are laterally offset from one another and vertically spaced apart from one another”. For this reason, claims 25-26 are rejected for including the same limitation of Claim 1 (US 12074024B2).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 16-20 are rejected under 35 U.S.C. 112(a), as failing to comply with the written description requirement. The claim 16 contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention. The claimed subject matter “wherein all of the plurality of first buried oxide layers are separated from one another, and laterally and vertically spaced apart from one another”. The claimed position of “all of the plurality of first buried oxide layers are laterally and vertically spaced apart from one another” are not described in the Disclosure, in specific “laterally space apart”. The specification does not contain the subject matter described in the claimed invention. For the examination purpose, the limitation “wherein all of the plurality of first buried oxide layers are separated from one another, and laterally and vertically spaced apart from one another” is interpreted as “wherein all of the plurality of first buried oxide layers are separated from one another, and spaced apart from one another”.
Regarding Claims 17-20, those are rejected under 35 U.S.C. 112 (a), because of their dependency status from claim 16.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second
paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 16, it recites the limitation “wherein all of the plurality of first buried oxide layers are separated from one another, and laterally and vertically spaced apart from one another”. It is not clear how all of the plurality of first buried oxide layers are laterally and vertically spaced apart from one another. The limitation is not explained and it does not show in the drawings. Therefore, it is indefinite. For the examination purpose, the limitation “wherein all of the plurality of first buried oxide layers are separated from one another, and laterally and vertically spaced apart from one another” is interpreted as “wherein all of the plurality of first buried oxide layers are separated from one another, spaced apart from one another”.
Regarding claims 17-20, those are rejected under 35 U.S.C. 112 (b), because of their dependency status from claim 16.
Re: claim 18, it recites the limitation “…wherein each of the first oxide layer and the second oxide layer has a sidewall…” is not explained. The limitation has an antecedent issue of “the first oxide layer and the second oxide layer”. Therefore, it is indefinite. For the examination purpose and according to Fig. 4 and claim 16, the limitation “…wherein each of the first oxide layer and the second oxide layer has a sidewall” is interpreted as “…wherein each of the plurality of first buried oxide layers has a sidewall…”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 3, 5-7, 16 and 19-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim et al. (US 20050176219 A1, hereinafter Kim).
Re: Independent Claim 1, Kim discloses a semiconductor device, comprising:
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Kim’s Figure 11-Annotated.
a transistor (MOSFET in [0026], Fig. 11) comprising a gate structure (180-170 in [0051], Fig. 11), a first source/drain (195-190-left forms source/drain regions of the MOSFET in [0052], Fig. 11) structure, and a second source/drain structure (195-190-rigth forms source/drain regions of the MOSFET in [0052], Fig. 11),
wherein the gate structure (180-170) is laterally disposed between the first source/drain structure (195-190-left) and the second source/drain structure (195-190-rigth),
wherein the first source/drain structure (195-190-left) and the second source/drain structure (195-190-rigth) are formed in a first silicon layer (130 epitaxial semiconductor layer in [0040], Fig. 11) disposed over a second silicon layer (100 semiconductor layer made of silicon in [0013], Fig. 11), the first silicon layer (130) having at least a portion in direct contact (Fig. 11) with the second silicon layer (100), and
wherein the second silicon layer (100) includes a plurality of buried oxide layers (150-160-left and 150-160-right in 201, a device isolation pattern 160 and a thermal oxide layer 150 in [0049, 0062, 0065], Fig. 11).
Re: Claim 3, Kim discloses the semiconductor device of claim 1, wherein the first silicon layer (130) is an epitaxial layer (in [0040], Fig. 11).
Re: Claim 5, Kim discloses the semiconductor device of claim 1, wherein a topmost one of the buried oxide layers (150-160-left in 201) is in contact with at least one of the first source/drain structure (195-190-left) or second source/drain structure.
Re: Claim 6, Kim discloses the semiconductor device of claim 1, wherein the plurality of buried oxide layers (150-160-left and 150-160-right in 201) are separated from or connected to one another (Fig. 11).
Re: Claim 7, Kim discloses the semiconductor device of claim 1, wherein the second silicon layer (100) is an epitaxial layer ([0037]).
Re: Independent Claim 16, Kim teaches a semiconductor device, comprising:
a first silicon layer (100 semiconductor layer made of silicon in [0013], Fig. 11) comprising a plurality of first buried oxide layers (150-160-left and 150-160-right in 201, a device isolation pattern 160 and a thermal oxide layer 150 in [0049, 0062, 0065], Fig. 11) embedded therein; and
a second silicon layer (130 epitaxial semiconductor layer in [0040], Fig. 11) disposed over the first silicon layer (100), wherein all of the plurality of first buried oxide layers (150-160-left and 150-160-right in 201) are separated from one another (Fig. 11), and spaced apart from one another (150-160-left and 150-160-right in 201 are spaced part by portions of 100, Fig. 11).
Re: Claim 19, Kim discloses the semiconductor device of claim 16, further comprising a first (195-190-left forms source/drain regions of the MOSFET in [0052], Fig. 11) and a second (195-190-rigth forms source/drain regions of the MOSFET in [0052], Fig. 11) source/drain structures in the second silicon layer (130).
Re: Claim 20, Kim discloses the semiconductor device of claim 19, further comprising a gate structure (180-170 in [0051], Fig. 11) disposed over the second silicon layer (130) and between the first source/drain structure (195-190-left) and second source/drain structure (195-190-rigth).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 8 and 17 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim in view of Cheng et al. (US 20080283918 A1, hereinafter Cheng).
Re: Claim 2, Kim discloses the semiconductor device of claim 1,
Kim does not expressly disclose vertical distances between the plurality of buried oxide layers and the first silicon layer, respectively, are different.
However, in the same semiconductor device field of endeavor, Cheng discloses vertical distances (D2 and D5, in Fig. 2, wherein BOX1-214 is located in a depth D2 below the top surface of 216 and two lower BOX2-226L is located in a depth D5 below the top surface of 216, in Fig. 2) between the plurality of buried oxide layers (BOX1-214 and two lower BOX2-226L) and the first silicon layer (216, Fig. 2), respectively, are different (D2 and D5 has positioned at different vertical distance as showed in Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Cheng’s feature of vertical distances between the plurality of buried oxide layers and the first silicon layer, respectively, are different to Kim’s device to increase channel strain and higher performance ([0011], Cheng).
Re: Claim 8, Kim discloses the semiconductor device of claim 1, further comprising at least one second buried oxide layer embedded in the second silicon layer.
Kim does not expressly disclose further comprising at least one second buried oxide layer embedded in the second silicon layer.
However, in the same semiconductor device field of endeavor, Cheng discloses further comprising at least one second buried oxide layer (two lower BOX2-226L in Fig. 2) embedded in the second silicon layer (216 in [0061], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Cheng’s feature of further comprising at least one second buried oxide layer embedded in the second silicon layer to Kim’s device to increase channel strain and higher performance ([0011], Cheng).
Re: Claim 17, Kim discloses the semiconductor device of claim 16,
Kim does not expressly disclose wherein vertical distances between the plurality of first buried oxide layers and the second silicon layer, respectively, are different.
However, in the same semiconductor device field of endeavor, Cheng discloses vertical distances (D2 and D5, in Fig. 2, wherein BOX1-214 is located in a depth D2 below the top surface of 216 and two lower BOX2-226L is located in a depth D5 below the top surface of 216, in Fig. 2) between the plurality of first buried oxide layers (BOX1-214 and two lower BOX2-226L) and the second silicon layer (216, Fig. 2), respectively, are different (D2 and D5 has positioned at different vertical distance as showed in Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Cheng’s feature of wherein vertical distances between the plurality of first buried oxide layers and the second silicon layer, respectively, are different to Kim’s device to increase channel strain and higher performance ([0011], Cheng).
Claim(s) 21, 23-24 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20080283918 A1, hereinafter Cheng) in view of Shin (US 20090001468 A1, hereinafter Shin).
Re: Independent Claim 21, Cheng discloses a semiconductor device, comprising:
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Cheng’s Figure 2-Annotated.
a transistor (transistor with gate conductor GC in [0014], Fig. 2) comprising a gate structure (gate conductor GC and a gate dielectric layer GD in [0014, 0058], Fig. 2), a channel (CH a channel in [0042], Fig. 2), a first source/drain structure (216-left source and drain regions in [0061], Fig. 2), and a second source/drain structure (216-rigth source and drain regions in [0061], Fig. 2); and
a first buried oxide layer (BOX2-226U in [0052], Fig. 2) and a second buried oxide layer (BOX1 -BOX2-226L in [0052], Fig. 2) disposed below the transistor (Fig. 2), the first buried oxide layer (BOX2-226U) and the second buried oxide layer (BOX1 -BOX2-226L) being vertically disposed with respect to each other (Fig. 2),
wherein the first buried oxide layer (BOX2-226U) includes at least a portion overlapped (BOX2-226U overlap with a top portion of BOX1 -BOX2-226L) with the second buried oxide layer (BOX1 -BOX2-226L), when viewed from the top.
Cheng does not expressly disclose the transistor being surrounded by a shallow trench isolation structure.
However, in the same semiconductor device field of endeavor, Shin discloses a transistor (MOS transistor in [0047], Fig. 11) being surrounded by a shallow trench isolation structure (106 the isolation layer in [0050], Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Shin’s feature of a transistor being surrounded by a shallow trench isolation structure to Cheng’s device to isolate between semiconductor devices ([0050], Shin).
Re: Claim 23, Kim modified by Shin discloses the semiconductor device of claim 21, wherein the second buried oxide layer (BOX1 -BOX2-226L, Kim) is in contact with the shallow trench isolation structure (Shin’s 106 applied to Kim, Fig. 11 from Shin).
Re: Claim 24, Kim modified by Shin discloses the semiconductor device of claim 21, wherein the first buried oxide layer (BOX2-226U, Kim), disposed over the second buried oxide layer (BOX1 -BOX2-226L, Kim), is in contact with the channel (CH, Kim).
Claim 1 rejected by Zhu and Lebby.
Claim(s) 1 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Zhu (US 20050285192 A1, hereinafter Zhu) in view of Lebby et al. (US 20080135924 A1, hereinafter Lebby).
Re: Independent Claim 1, Zhu discloses a semiconductor device, comprising:
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Zhu’s Figure 2-Annotated.
a transistor (MOSFET in [0009], Fig. 2) comprising a gate structure (110-103 in [0023], Fig. 2), a first source/drain (40-left forms source/drain regions of the MOSFET in [0023], Fig. 2-Annotated) structure, and a second source/drain structure (40-right forms source/drain regions of the MOSFET in [0023], Fig. 2-Annotated),
wherein the gate structure (110-103) is laterally disposed between the first source/drain structure (40-left) and the second source/drain structure (40-rigth),
wherein the first source/drain structure (40-left) and the second source/drain structure (40-rigth) are formed in a first silicon layer (30 silicon layer in [0023], Fig. 2) disposed over a second silicon layer (10-35 made of silicon in [0049, 0054], Fig. 2), the first silicon layer (30) having at least a portion in direct contact (10-35 is contact by portion 35 with layer 30 Fig. 2) with the second silicon layer (10-35), and
wherein the second silicon layer (10-35) includes a buried oxide layer (20 in [0026], Fig. 2).
Zhu does not expressly disclose wherein the second silicon layer (10-35) includes a plurality of buried oxide layers.
However, in the same semiconductor device field of endeavor, Lebby discloses wherein the second silicon layer (substrate made of silicon in [0063], Fig. 20) includes a plurality of buried oxide layers (30’ a structure including a plurality of boxes layers in [0057], Fig. 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lebby’s feature of wherein the second silicon layer includes a plurality of buried oxide layers to Zhu’s device for controlling short channel effects and/or leakage and/or threshold effects of FDSOI MOSFETs advantageously using multilayer thin BOX ([0024], Lebby).
Claim(s) 4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Zhu (US 20050285192 A1, hereinafter Zhu) in view of Lebby et al. (US 20080135924 A1, hereinafter Lebby) and further in view of Shin (US 20090001468 A1, hereinafter Shin).
Re: Claim 4, Zhu modified by Lebby discloses the semiconductor device of claim 1,
Zhu modified by Lebby does not expressly disclose further comprising a shallow trench isolation structure surrounding the transistor, wherein each of the plurality of buried oxide layers has at least one sidewall in contact with the shallow trench isolation structure.
However, in the same semiconductor device field of endeavor, Shin discloses a shallow trench isolation structure (106 the isolation layer in [0050], Fig. 12) surrounding the transistor (MOS transistor in [0047], Fig. 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Shin’s feature of a shallow trench isolation structure surrounding the transistor to the combination of Zhu and Lebby to obtain wherein each of the plurality of buried oxide layers has at least one sidewall in contact with the shallow trench isolation structure to isolate between semiconductor devices ([0050], Shin).
Claim 16 rejected by Zhu and Lebby.
Claim(s) 16 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Zhu (US 20050285192 A1, hereinafter Zhu) in view of Lebby et al. (US 20080135924 A1, hereinafter Lebby).
Re: Independent Claim 16, Zhu discloses a semiconductor device, comprising:
a first silicon layer (10-35 made of silicon in [0049, 0054], Fig. 2) comprising a first buried oxide layer (20 in [0026], Fig. 2) embedded therein; and
a second silicon layer (30 silicon layer in [0023], Fig. 2) disposed over the first silicon layer (10-35).
Zhu does not expressly disclose a first silicon layer (10-35) comprising a plurality of first buried oxide layers embedded therein; and wherein all of the plurality of first buried oxide layers are separated from one another and spaced apart from one another.
However, in the same semiconductor device field of endeavor, Lebby discloses a first silicon layer (substrate made of silicon in [0063], Fig. 20) comprising a plurality of first buried oxide layers (BOX 1 and BOX 3 as part of a structure 30’ including a plurality of boxes layers in [0057], Fig. 20) embedded therein; and wherein all of the plurality of first buried oxide layers (BOX 1 and BOX 3) are separated from one another (Fig. 20), and spaced apart from one another (Fig. 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lebby’s feature of a first silicon layer comprising a plurality of first buried oxide layers embedded therein; and wherein all of the plurality of first buried oxide layers are separated from one another, and spaced apart from one another to Zhu’s device for controlling short channel effects and/or leakage and/or threshold effects of FDSOI MOSFETs advantageously using multilayer thin BOX ([0024], Lebby).
Claim(s) 18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Zhu in view of Lebby and further in view of Shin (US 20090001468 A1, hereinafter Shin).
Re: Claim 18, Zhu modified by Lebby discloses the semiconductor device of claim 16,
Zhu modified by Lebby does not expressly disclose further comprising a shallow trench isolation structure surrounding the first silicon layer, wherein each of wherein each of the plurality of first buried oxide layers has a sidewall in contact with the shallow trench isolation structure.
However, in the same semiconductor device field of endeavor, Shin discloses a shallow trench isolation structure (106 the isolation layer in [0050], Fig. 12) surrounding first silicon layer (104a silicon layer in [0049], Fig. 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Shin’s feature of a shallow trench isolation structure surrounding the first silicon layer to the combination of Zhu and Lebby to obtain wherein each of the plurality of first buried oxide layers has a sidewall in contact with the shallow trench isolation structure to isolate between semiconductor devices ([0050], Shin).
Claims 21-22 rejected by Zhu, Shin and Lebby.
Claim(s) 21-22 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Zhu in view of Shin and further in view of Lebby.
Re: Independent Claim 21, Zhu discloses a semiconductor device, comprising:
a transistor (MOSFET in [0009], Fig. 1) comprising a gate structure (110-103 in [0023], Fig. 1), a channel (a top portion of layer 30 as a channel in [0023], Fig. 1), a first source/drain structure (40-left forms source/drain regions of the MOSFET in [0023], Fig. 1), and a second source/drain structure (40-right forms source/drain regions of the MOSFET in [0023], Fig. 1); and
a first buried oxide layer (20 in [0026], Fig. 2) disposed below the transistor ([0009], Fig. 1).
Zhu does not expressly disclose the transistor being surrounded by a shallow trench isolation structure and a second buried oxide layer disposed below the transistor, the first buried oxide layer and the second buried oxide layer being vertically disposed with respect to each other, wherein the first buried oxide layer includes at least a portion overlapped with the second buried oxide layer, when viewed from the top.
However, in the same semiconductor device field of endeavor, Shin discloses a transistor (MOS transistor in [0047], Fig. 11) being surrounded by a shallow trench isolation structure (106 the isolation layer in [0050], Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Shin’s feature of a transistor being surrounded by a shallow trench isolation structure to Zhu’s device to isolate between semiconductor devices ([0050], Shin).
Zhu modified by Shin does not expressly disclose a second buried oxide layer disposed below the transistor, the first buried oxide layer and the second buried oxide layer being vertically disposed with respect to each other, wherein the first buried oxide layer includes at least a portion overlapped with the second buried oxide layer, when viewed from the top.
However, in the same semiconductor device field of endeavor, Lebby discloses a second buried oxide layer (BOX 2 as part of a structure 30’ including a plurality of boxes layers in [0057], Fig. 20) disposed below the transistor (MOSFET transistor in [0057], Fig. 20), the first buried oxide layer (BOX 1 as part of a structure 30’ including a plurality of boxes layers in [0057], Fig. 20) and the second buried oxide layer (BOX 2) being vertically disposed with respect to each other (Fig. 20), wherein the first buried oxide layer (BOX 1) includes at least a portion overlapped with the second buried oxide layer (BOX 2), when viewed from the top.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lebby’s feature of a second buried oxide layer disposed below the transistor, the first buried oxide layer and the second buried oxide layer being vertically disposed with respect to each other, wherein the first buried oxide layer includes at least a portion overlapped with the second buried oxide layer, when viewed from the top to the combination of Zhu and Shin for controlling short channel effects and/or leakage and/or threshold effects of FDSOI MOSFETs advantageously using multilayer thin BOX ([0024], Lebby).
Re: Claim 22, Zhu modified by Shin and Lebby discloses the semiconductor device of claim 21, wherein the first buried oxide layer (Lebby’s BOX 1 applied to Zhu), disposed over the second buried oxide layer (Lebby’s BOX 2 applied to Zhu), is in contact with at least one of the first source/drain structure (40-left forms source/drain regions of the MOSFET in [0023], Fig. 1, Zhu) or second source/drain structure.
Allowable Subject Matter
Claims 25-26 are objected to as being dependent upon a rejected base claim, but would
be allowable if rewritten in independent form including all of the limitations of the base claim 1 and any intervening claims.
Re: claim 25, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner's knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: recited features of the device of claim 21, “…further comprising a third buried oxide layer disposed below the transistor, and vertically spaced from the first buried oxide layer and the second buried oxide layer…” as recited in claim 25, in combination with remaining features of base claim 21.
Re: claim 26, this inherits the allowable subject matter from claim 25.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Mariani et al. (US 20200058540 A1) teaches “SEMICONDUCTOR STRUCURE WITH PARTIALLY EMBEDDED INSULATION REGION”. This document is related to a technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.
Hamada (US 20190198607 A1) teaches “SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SAME”. This document is related to a semiconductor device includes an emitter region, a base contact region, a buried region, and a carrier trap region. The emitter region and the base contact region are selectively disposed in the upper surface of the base region while being adjacent to each other. The buried region is disposed in the drift region below the base contact region or the emitter region. The carrier trap region is disposed between the buried region and the base region, and has a carrier lifetime shorter than that of the drift region. The device can improve latch-up breakdown tolerance.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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