DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/17/2024, 10/21/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 11-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 11-14 of U.S. Patent No. 12,125,922. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 11, Pat '922 discloses, in claim 11, a semiconductor device comprising:
a fin protruding above a substrate; a gate structure over the fin; source/drain regions over the fin on opposite sides of the gate structure (all limitations are the same with the limitations recited in claim 11 of Pat '922);
a first channel layer and a second channel layer disposed between the source/drain regions, wherein the gate structure wraps around the first channel layer and the second channel layer; and an inner spacer disposed between the first channel layer and the second channel layer, wherein the inner spacer has a first curved surface facing the gate structure, and has a second curved surface facing the source/drain regions, wherein a thickness of the inner spacer, measured between the first curved surface and the second curved surface, increases along a direction from a center location between the first channel layer and the second channel layer toward an interface between the inner spacer and the first channel layer ("a first channel layer and a second channel layer disposed between the source/drain regions and parallel to each other, wherein the gate structure wraps around the first channel layer and the second channel layer; and inner spacers disposed between end portions of the first channel layer and end portions of the second channel layer, wherein each of the inner spacers has a first curved surface facing the gate structure, and has a second curved surface facing the source/drain regions, wherein a thickness of a first inner spacer of the inner spacers, measured between the first curved surface and the second curved surface of the first inner spacer, has a smallest value at a center location between the first channel layer and the second channel layer, and has a largest value at an interface between the first inner spacer and the first channel layer", in claim 11 of Pat '922, is interpreted as the same limitation).
Regarding claim 12, Pat '922 in view of Wang discloses the semiconductor device of claim 11 as described above.
Pat '922 further discloses, in claim 12 an air gap between the inner spacer and the source/drain regions ("air gaps between the inner spacers and the source/drain regions", in claim 12 of Pat '922, is interpreted as the same limitation).
Regarding claim 13, Pat '922 in view of Wang discloses the semiconductor device of claim 12 as described above.
Pat '922 in view of Wang does not explicitly disclose the air gap has an upper portion and a lower portion that is separated from the upper portion.
Pat '922 teaches, in claim 1, the air gap has an upper portion and a lower portion that is separated from the upper portion ("each air gap comprises an upper portion and a lower portion that is separated from the upper portion", in claim 1 of Pat '922, is interpreted as the same limitation), for the purpose of providing air gaps to reduce the parasitic capacitance of the device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '922 in view of Wang to have the air gap having an upper portion and a lower portion that is separated from the upper portion, as taught by claim 1 of Pat '922, for the purpose of providing air gaps to reduce the parasitic capacitance of the device.
Regarding claim 14, Pat '922 in view of Wang discloses the semiconductor device of claim 13 as described above.
Pat '922 further discloses, in claim 13, a material layer between the inner spacer and the source/drain regions, wherein the air gap is between the inner spacer and the material layer ("a material layer between the inner spacers and the source/drain regions, wherein the air gaps are between the inner spacers and the material layer", in claim 13 of Pat '922, is interpreted as the same limitation).
Regarding claim 15, Pat '922 in view of Wang discloses the semiconductor device of claim 14 as described above.
Pat '922 further discloses, in claim 14, the material layer has a third curved surface that contacts the second curved surface of the inner spacer, and has a fourth curved surface that contacts the source/drain regions ("the material layer has a third curved surface that contacts the second curved surface of each of the inner spacers, and has a fourth curved surface that faces a respective source/drain region ", in claim 14 of Pat '922, is interpreted as the same limitation).
Claims 1-5 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, 9-10 and 18 of U.S. Patent No. 12,125,922 in view of Wang (US 2021/0126106).
Regarding claim 1, Pat '922 discloses, in claim 1, a semiconductor device comprising:
a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions (all limitations are the same with the limitations recited in claim 1 of Pat '922);
a gate structure between the source/drain regions ("a gate structure over the fin and between the source/drain regions", in claim 1 of Pat '922, is interpreted as the same limitation);
each air gap of the air gaps comprises an upper portion and a lower portion separated from the upper portion ("each air gap comprises an upper portion and a lower portion that is separated from the upper portion", in claim 1 of Pat '922, is interpreted as the same limitation).
Pat '922 does not explicitly disclose a gate structure around the nanosheets; inner spacers laterally between the gate structure and the source/drain regions; air gaps laterally between the inner spaces and the source/drain regions.
Wang teaches, in at least figures 1-2B and related text, the device comprising a gate structure (210, [43]) around the nanosheets (122, [26]); inner spacers (212, [50]) laterally between the gate structure (210, [43]) and the source/drain regions (224, [50]); air gaps (214, [50]) laterally between the inner spaces (212, [50]) and the source/drain regions (224, [50]), for the purpose of reducing effectively the overall dielectric constant of the inner spacer, reducing gate-to-source/drain coupling effects in the nano-sheet FET and improving device performance (e.g., speed) of the IC ([21]).
Pat '922 and Wang are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '922 with the specified features of Wang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '922 to have the a gate structure around the nanosheets; the inner spacers laterally between the gate structure and the source/drain regions; the air gaps laterally between the inner spaces and the source/drain regions, as taught by Wang, for the purpose of reducing effectively the overall dielectric constant of the inner spacer, reducing gate-to-source/drain coupling effects in the nano-sheet FET and improving device performance (e.g., speed) of the IC ([21], Wang).
Regarding claim 2, Pat '922 in view of Wang discloses the semiconductor device of claim 1 as described above.
Pat '922 further discloses, in claim 1, the air gaps are disposed laterally between the material layer and the inner spacers ("each air gap is disposed laterally between an inner spacer and the material layer", in claim 1 of Pat '922, is interpreted as the same limitation).
Wang further teaches, in at least figures 1-2B and related text, a material layer (216, [50]) laterally between the inner spacers (212, [50]) and the source/drain regions (224, [50]), for the purpose of reducing effectively the overall dielectric constant of the inner spacer, reducing gate-to-source/drain coupling effects in the nano-sheet FET and improving device performance (e.g., speed) of the IC ([21]).
Regarding claim 3, Pat '922 in view of Wang discloses the semiconductor device of claim 2 as described above.
Pat '922 further discloses, in claim 9, the material layer is a semiconductor material (all limitations are the same with the limitations recited in claim 9 of Pat '922).
Regarding claim 4, Pat '922 in view of Wang discloses the semiconductor device of claim 2 as described above.
Pat '922 further discloses, in claim 10, the material layer is a dielectric material (all limitations are the same with the limitations recited in claim 10 of Pat '922).
Regarding claim 5, Pat '922 in view of Wang discloses the semiconductor device of claim 2 as described above.
Pat '922 further discloses, in claim 7, each inner spacer of the inner spacers has a first curved surface facing the material layer, and has a second curved surface facing the gate structure ("each of the inner spacers has a first curved surface facing the material layer, and has a second curved surface facing the gate structure", in claim 7 of Pat '922, is interpreted as the same limitation).
Regarding claim 17, Pat '922 discloses, in claim 18, a method of forming a semiconductor device, the method comprising: forming a dummy gate structure over a nanostructure, wherein the nanostructure overlies a fin that protrudes above a substrate, and the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure; forming dummy inner spacers in the recesses (all limitations are the same with the limitations recited in claim 18 of Pat '922);
forming source/drain regions in the openings after forming the dummy inner spacers; after forming the source/drain regions, removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; removing the exposed first semiconductor material and the dummy inner spacers, wherein the second semiconductor material under the dummy gate structure remains to form nanosheets; and after removing the exposed first semiconductor material and the dummy inner spacers, forming inner spacers between adjacent ones of the nanosheets ("forming a material layer in the recess on the dummy inner spacers; forming source/drain regions in the openings after forming the material layer; after forming the source/drain regions, removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material disposed under the dummy gate structure; performing an etching process to remove the exposed first semiconductor material and the dummy inner spacers, wherein the second semiconductor material under the dummy gate structure remains to form a plurality of nanosheets; and after performing the etching process, forming inner spacers between end portions of adjacent ones of the plurality of nanosheets", in claim 18 of Pat '922, is interpreted as the same limitation).
Pat '922 does not explicitly disclose forming recesses in sidewalls of the first semiconductor material exposed by the openings.
Wang teaches, in at least figures 9-10 and related text, the method comprising forming recesses in sidewalls of the first semiconductor material (1018, [77]) exposed by the openings (space under 736, figures), for the purpose of reducing effectively the overall dielectric constant of the inner spacer, reducing gate-to-source/drain coupling effects in the nano-sheet FET and improving device performance (e.g., speed) of the IC ([21]).
Pat '922 and Wang are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '922 with the specified features of Wang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '922 to have the forming recesses in sidewalls of the first semiconductor material exposed by the openings, as taught by Wang, for the purpose of reducing effectively the overall dielectric constant of the inner spacer, reducing gate-to-source/drain coupling effects in the nano-sheet FET and improving device performance (e.g., speed) of the IC ([21], Wang).
Claims 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 18 of U.S. Patent No. 12,125,922 in view of Wang (US 2021/0126106), and further in view of claims 19-20 of U.S. Patent No. 11,791,421.
Regarding claim 18, Pat '922 in view of Wang discloses the method of claim 17 as described above.
Pat '922 in view of Wang does not explicitly disclose after forming the dummy inner spacers and before forming the source/drain regions, forming a material layer in the recesses along sidewalls of the dummy inner spacers.
Pat '421 teaches, in claim 20, after forming the dummy inner spacers and before forming the source/drain regions, forming a material layer in the recesses along sidewalls of the dummy inner spacers ("after forming the dummy inner spacers and before forming the source/drain regions, forming a material layer in the recesses along the dummy inner spacers, wherein the air gaps are formed between the inner spacers and the material layer", in claim 20 of Pat '421, is interpreted as the same limitation), for the purpose of providing air gaps to reduce the parasitic capacitance of the device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '922 in view of Wang to have after forming the dummy inner spacers and before forming the source/drain regions, the forming a material layer in the recesses along sidewalls of the dummy inner spacers, as taught by claim 20 of Pat '421, for the purpose of providing air gaps to reduce the parasitic capacitance of the device.
Regarding claim 19, Pat '922 in view of Wang and Pat '421 discloses the method of claim 18 as described above.
Pat '922 further discloses, in claims 19-20, after forming the inner spacers, air gaps are sealed between the inner spacers and the material layer ("after the etching process, forming an inner spacer layer to line surfaces of the nanosheets and to line surfaces of the material layer exposed by the removal of the dummy inner spacers; and performing another etching process to remove first portions of the inner spacer layer, wherein second portions of the inner spacer layer contacting the material layer remain to form the inner spacers" and “after the another etching process, air gaps are sealed between the inner spacers and the material layer”, in claims 19 and 20 of Pat '922, are interpreted as the same limitation).
Regarding claim 20, Pat '922 in view of Wang discloses the method of claim 17 as described above.
Wang further teaches, in at least figures 2A-2B, 18, and related text, after forming the inner spacers (208, [50]), forming a gate structure (210, [89]) around the nanosheets (122, [27]), for the purpose of reducing effectively the overall dielectric constant of the inner spacer, reducing gate-to-source/drain coupling effects in the nano-sheet FET and improving device performance (e.g., speed) of the IC ([21]).
Allowable Subject Matter
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 2, 5, and 6 that recite "a middle region of the first curved surface contacts the material layer, and peripheral regions of the first curved surface are spaced apart from the material layer" in combination with other elements of the base claims 1, 2, 5, and 6.
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 2, 5, and 8 that recite "a distance, measured between the first curved surface and the second curved surface of each inner spacer, increases then decreases along a direction from an upper surface of each inner spacer distal from the substrate toward a lower surface of each inner spacer facing the substrate" in combination with other elements of the base claims 1, 2, 5, and 8.
Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 2, and 9 that recite "a width of the upper portion of an air gap disposed between an inner spacer and the material layer, measured between the inner spacer and the material layer, increases as the upper portion of the air gap extends along a first direction away from a center location of the inner spacer, wherein the first direction is perpendicular to a major upper surface of the substrate, and the center location of the inner spacer is between two adjacent nanosheets or between a lowermost nanosheet and the fin" in combination with other elements of the base claims 1, 2, and 9.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 11, 12, 14, 15, and 16 that recite "there is no gap between the source/drain regions and the fourth curved surface" in combination with other elements of the base claims 11, 12, 14, 15, and 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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