Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/17/24, 10/16/24 were filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims #1-5, 7-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims #1-9, 11-13, 15, 17-20 of Fan et al., (U.S. Patent No. U.S. 12,100,751), hereinafter referred to as "Fan". Although the claims at issue are not identical, they are not patentably distinct from each other because;
Claim #1 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #1 of U.S. Patent No. 12,100,751, which discloses, method of forming a semiconductor device, the method comprising: forming a dummy gate over a fin, wherein the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, wherein replacing the dummy gate comprises: forming a gate trench in the dielectric material by removing the dummy gate; forming a metal-gate stack in the gate trench by forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench, wherein there is a cavity in the gap-filling material; and after forming the metal-gate stack, removing the cavity in the gap-filling material. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #1, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #1 of the instant application, which states, a method of forming a semiconductor device, the method comprising: forming a dummy gate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate, wherein replacing the dummy gate comprises: removing the dummy gate to form a trench in the dielectric material; forming a gate dielectric layer, a work function layer, and a gap-filling material sequentially in the trench, wherein after forming the gap-filling material, there is a cavity in the gap-filling material; and removing the cavity in the gap-filling material.
Claim #2 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #2 of U.S. Patent No. 12,100,751, which discloses, method wherein removing the cavity comprises enlarging a volume of the gap-filling material, and the cavity is filled by the gap-filling material with the enlarged volume. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #2, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #2 of the instant application, which states, a method wherein removing the cavity comprises enlarging a volume of the gap-filling material, wherein the cavity is filled by the gap-filling material with the enlarged volume.
Claim #3 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #4 of U.S. Patent No. 12,100,751, which discloses, method wherein removing the cavity comprises treating the gap-filling material with a fluorine-containing chemical. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #4, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #3 of the instant application, which states, a method wherein enlarging the volume of the gap-filling material comprises treating the gap-filling material using a fluorine-containing chemical.
Claim #4 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #5 of U.S. Patent No. 12,100,751, which discloses, method wherein treating the gap-filling material comprises treating the gap-filling material with a thermal process using a fluorine-containing gas. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #5, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #4 of the instant application, which states, a method wherein treating the gap-filing material comprises treating the gap-filing material with a thermal process using a fluorine-containing gas.
Claim #5 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #6 of U.S. Patent No. 12,100,751, which discloses, method wherein treating the gap-filling material comprises treating the gap-filling material with a plasma process using a plasma of a fluorine-containing gas. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #6, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #5 of the instant application, which states, a method wherein treating the gap-filling material comprises treating the gap-filling material with a plasma process using a plasma of a fluorine-containing gas.
Claim #16 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #6 of U.S. Patent No. 12,100,751, which discloses, method wherein treating the gap-filling material comprises treating the gap-filling material with a plasma process using a plasma of a fluorine-containing gas. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #6, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #16 of the instant application, which states, a method wherein treating the conductive material comprises supplying a fluorine-containing gas to the conductive material in a thermal process.
Claim #7 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #3 of U.S. Patent No. 12,100,751, which discloses, method wherein the gap-filling material is formed of an aluminum-containing material. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #3, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #7 of the instant application, which states, a method wherein the gap-filling material is an aluminum-containing material.
Claim #8 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #7 of U.S. Patent No. 12,100,751, which discloses, method wherein after treating the gap-fill material, the gap-fill material comprises aluminum fluoride. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #7, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #8 of the instant application, which states, a method wherein the fluorine-containing chemical reacts with the gap-filling material to form aluminum fluoride.
Claim #9 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #8 of U.S. Patent No. 12,100,751, which discloses, method wherein after treating the gap-fill material, the first work function layer is free of fluoride. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #8, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #9 of the instant application, which states, a method wherein after treating the gap-filling material, the work function layer is free of fluoride.
Claim #10 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #9 of U.S. Patent No. 12,100,751, which discloses, method wherein after treating the gap-fill material, a first portion of the first work function layer contacting the gap-fill material comprises fluoride, and a second portion of the first work function layer distal from the gap-fill material is free of fluoride. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #9, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #10 of the instant application, which states, a method wherein after treating the gap-filling material, a first portion of the work function layer contacting the gap-filling material comprises fluoride, and a second portion of the work function layer distal from the gap-filling material is free of fluoride.
Claim #11 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #11 of U.S. Patent No. 12,100,751, which discloses, method further comprising: recessing an upper surface the metal-gate stack below an upper surface of the dielectric material distal from the substrate; forming a capping layer over the recessed metal-gate stack; and forming a gate contact in the dielectric material over the capping layer. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #11, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #11 of the instant application, which states, a method further comprising, after replacing the dummy gate: recessing the gate dielectric layer, the work function layer, and the gap-filling material below an upper surface of the dielectric material; forming a capping layer over the recessed work function layer and the recessed gap-filling material; and forming a gate contact in the dielectric material over the capping layer.
Claim #12 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #12 of U.S. Patent No. 12,100,751, which discloses, method wherein the capping layer is formed of tungsten. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #12, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #12 of the instant application, which states, a method wherein the capping layer is formed of tungsten.
Claim #13 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #13 of U.S. Patent No. 12,100,751, which discloses, method of forming a semiconductor device, the method comprising: surrounding a dummy gate with a dielectric layer; removing the dummy gate to form a trench in the dielectric layer; lining sidewalls and a bottom of the trench with a gate dielectric layer; forming one or more work function layers over the gate dielectric layer; filling the trench with a conductive material, wherein after filling the trench, there is a gap in the conductive material; and after filling the trench, treating the conductive material to expand a volume of the conductive material. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #13, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #13 of the instant application, which states, a method of forming a semiconductor device, the method comprising: surrounding a dummy gate with a dielectric layer; removing the dummy gate to form a trench in the dielectric layer; lining sidewalls and a bottom of the trench with a gate dielectric layer; forming one or more work function layers over the gate dielectric layer; filling the trench with a conductive material, wherein after filling the trench, there is a gap in the conductive material; and after filling the trench, expanding a volume of the conductive material to remove the gap.
Claim #14 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #15 of U.S. Patent No. 12,100,751, which discloses, method wherein the conductive material is formed of an aluminum-containing material, and treating the conductive material comprises treating the conductive material with a fluorine-containing chemical. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #15, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #14 of the instant application, which states, a method wherein expanding the volume of the conductive material comprises treating the conductive material with a fluorine-containing chemical.
Claim #15 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #15 of U.S. Patent No. 12,100,751, which discloses, method wherein the conductive material is formed of an aluminum-containing material, and treating the conductive material comprises treating the conductive material with a fluorine-containing chemical. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #15, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #15 of the instant application, which states, a method wherein the conductive material is formed of an aluminum-containing material.
Claim #17 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #17 of U.S. Patent No. 12,100,751, which discloses, method wherein treating the conductive material comprises: igniting a fluorine-containing gas into a plasma of the fluorine-containing gas; and supplying the plasma of the fluorine-containing gas to the conductive material. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #17, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #17 of the instant application, which states, a method wherein treating the conductive material comprises: igniting a fluorine-containing gas into a plasma; and supplying the plasma to the conductive material.
Claim #18 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #18 of U.S. Patent No. 12,100,751, which discloses, a semiconductor device comprising: a substrate; a fin protruding above the substrate; a gate structure over the fin, wherein the gate structure comprises: a gate dielectric layer; a work function layer over the gate dielectric layer; and an electrically conductive material embedded in the work function layer, wherein the electrically conductive material comprises aluminum and fluorine; and a capping layer over and contacting the work function layer and the electrically conductive material. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #18, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #18 of the instant application, which states, a method semiconductor device comprising: a substrate; a fin protruding above the substrate; a gate structure over the fin, wherein the gate structure comprises: a gate dielectric layer; a work function layer over the gate dielectric layer; and a gate electrode material over the work function layer, wherein the gate electrode material comprises aluminum and fluorine.
Claim #19 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #19 of U.S. Patent No. 12,100,751, which discloses, semiconductor device wherein the electrically conductive material extends from an upper surface of the work function layer into the work function layer. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #19, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #19 of the instant application, which states, wherein the work function layer surrounds the gate electrode material, wherein the gate electrode material extends from an upper surface of the work function layer distal from the substrate into the work function layer.
Claim #20 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #20 of U.S. Patent No. 12,100,751, which discloses, semiconductor device further comprising: a first gate spacer along a sidewall of the gate structure; and a second gate spacer along a sidewall of the first gate spacer, wherein the second gate spacer extends further from the substrate than the first gate spacer. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #20, of U.S. Patent No. 12,100,751, produces the same semiconductor structure as that in claim #20 of the instant application, which states, further comprising: a capping layer over and contacting the work function layer and the gate electrode material; a first gate spacer along a sidewall of the gate structure; and a second gate spacer along a sidewall of the first gate spacer facing away from the gate structure, wherein the second gate spacer extends further from the substrate than the first gate spacer.
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Claim #6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims #1-9, 11-13, 15, 17-20 of Fan et al., (U.S. Patent No. U.S. 12,100,751), hereinafter referred to as "Fan" as shown in the rejection of claim #7 above and in view of GHANI et al., (U.S. Pub. No. 2020/0335625), hereinafter referred to as “Ghani”.
Fan substantially shows the claimed invention as shown in the rejection of claim #7 above.
Fan fails to show, with respect to claim #6, a method wherein the fluorine-containing chemical is a gas source comprising nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), or fluorine (F2).
Ghani teaches, with respect to claim #6, a method wherein the fluorine-containing chemical is a gas source comprising nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), or fluorine (F2) (paragraph 0496).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #6, to modify the invention of Fan, with the modifications taught by Ghani’s invention, which teaches, wherein the fluorine-containing chemical is a gas source comprising nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), or fluorine (F2), to incorporate a condition that provides high-precision, anisotropic etching, surface modification, and device isolation capabilities that can improve performance, reliability, and manufacturability in semiconductor and advanced materials processing, as taught by Ghani.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683. The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson/
Art Unit 2899
09/14/2026
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights