DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/17/24 & 02/16/26 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 11-13, 17-18 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-13, 16-17 and 20 of U.S. Patent No. 12100640. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Claim 11 of this application and claim 11 of patent ‘640 are substantially similar except for the conductive bumps bonded to the first surface of the substrate recited in claim 11 of patent ‘640, but it would have been obvious to one skilled in the art to have provided the said conductive bumps in claim 11 of this application in order to electrically connect the interposer to the substrate. Claims 12 and 13 of this application are identical to respectively claim 12 and 13 of patent ‘640.
Claim 17 of this application and claim 16 of patent ‘640 are substantially similar except for the conductive bumps coupled to the first surface of the substrate recited in claim 16 of patent ‘640, but it would have been obvious to one skilled in the art to have provided the said conductive bumps in claim 17 of this application in order to electrically connect the interposer to the substrate. Claims 18 and 20 of this application are identical to respectively claim 18 and 20 of patent ‘640.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 2018/0350754, cited on IDS).
a. Re claim 1, Huang et al. disclose a method comprising: attaching a semiconductor structure (58 less bumps 54; see figs. 1-7B and related text; see remaining of disclosure for more details) to a first (top) surface of a substrate 60, wherein the semiconductor structure comprises: an interposer 40; a die 44 attached to a first (top) side of the interposer; and a molding material 48 on the first side of the interposer around the die, wherein a second opposing side of the interposer is attached to the first surface of the substrate (explicit on figs. 5-6); placing a thermal interface material (TIM) film 78 over the molding material and the die, wherein after the placing, the TIM film covers an upper surface of the molding material and an upper surface of the die, and a peripheral portion 78B of the TIM film extends laterally beyond sidewalls of the molding material (explicit on figs. 7A-B noting that placing TIM 78 over the molding material and the die involves all the TIM 78 attachment processes/states since it is placed on said molding and die in figs. 6-7B); and attaching a lid 70 (figs. 7A-B and related text) to the first surface of the substrate to form an enclosed space between the lid and the substrate, wherein after attaching the lid, the semiconductor structure and the TIM film are disposed in the enclosed space, and the TIM film is in contact with the lid.
b. Re claim 7, attaching the semiconductor structure comprises bonding conductive bumps 54 at the second opposing side of the interposer to conductive features 64 at the first surface of the substrate (figs. 5-7B).
Allowable Subject Matter
Claims 2-6, 8-10, 14-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hung (US 2020/0294817) disclose a structure and method of forming thereof similar to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899
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