Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on July 17, 2024, October 3, 2024, May 13, 2025, October 23, 2025 and January 27, 2026 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,070,875 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding Claim 1, Patent No.: US 12,070,875 B2 discloses
a silicon carbide (SiC) wafer comprising : a silicon face and a carbon face (claim 13); a diameter of at least 200 millimeters (mm) (claim 13); a relaxed positive bow from the silicon face (claim 13); and wherein a surface of the SiC wafer is not parallel to a crystallographic c-plane associated with the SiC wafer (claim 14).
Regarding Claim 2, Patent No.: US 12,070,875 B2, as applied to claim 1, discloses
the silicon carbide wafer, wherein a surface of the SiC wafer is misaligned with a crystallographic c-plane by an oblique angle relative to the crystallographic c-plane (claim 14).
Regarding Claim 3, Patent No.: US 12,070,875 B2, as applied to claim 2, discloses
the silicon carbide wafer, wherein the oblique angle is in a range from 1 to 10 degrees (claim 15).
Regarding Claim 4, Patent No.: US 12,070,875 B2, as applied to claim 2, discloses
the silicon carbide wafer, wherein the oblique angle is in a range from 2 to 6 degrees (claim 16).
Regarding Claim 5, Patent No.: US 12,070,875 B2, as applied to claim 2, discloses
the silicon carbide wafer, wherein the oblique angle is 4 degrees (claim 17).
Regarding Claim 6, Patent No.: US 12,070,875 B2, as applied to claim 1, discloses
the silicon carbide wafer, wherein the diameter is in a range from 200 mm to 205 mm (claim 18).
Regarding Claim 7, Patent No.: US 12,070,875 B2, as applied to claim 1, discloses
the silicon carbide wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to 50 µm (claim 14 together with 5).
Regarding Claim 8, Patent No.: US 12,070,875 B2, as applied to claim 1, discloses
the silicon carbide wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to 15 µm (claim 14 together with 6).
Regarding Claim 9, Patent No.: US 12,070,875 B2, as applied to claim 1, discloses
the silicon carbide wafer, wherein the relaxed positive bow is in a range including 30 µm to 50 µm (claim 14 together with 7).
Regarding Claim 10, Patent No.: US 12,070,875 B2, as applied to claim 1, discloses
the silicon carbide wafer, wherein the relaxed positive bow is in a range including 8 µm to 16 µm (claim 14 together with 8).
2. Claims 11-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US 12,070,875 B2, as applied to claim 1, in view of Swoboda et al. (Pub. No.: US 2020/0388538 A1).
Regarding Claim 11, Patent No.: US 12,070,875 B2, as applied to claim 1, does not explicitly disclose
the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio of at least 250.
However, Swoboda et al., at least implicitly, teaches the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio of at least 250 (Swoboda et al. – Par. 0167 together with Par. 0602). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Swoboda et al. to adapt the SiC wafer, wherein the SiC wafer of Patent No.: US 12,070,875 B2 comprises a diameter to thickness ratio of at least 250 in order to make sure that the wafer sag during epitaxial growth is countered by the positive bow of the wafer so that growth happens on a flat surface
Regarding Claim 12, Patent No.: US 12,070,875 B2, as applied to claim 1, does not explicitly disclose
the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio of at least 350.
However, Swoboda et al., at least implicitly, teaches the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio of at least 350 (Swoboda et al. – Par. 0167 together with Par. 0602). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Swoboda et al. to adapt the SiC wafer, wherein the SiC wafer of Patent No.: US 12,070,875 B2 comprises a diameter to thickness ratio of at least 350 in order to make sure that the wafer sag during epitaxial growth is countered by the positive bow of the wafer so that growth happens on a flat surface
Regarding Claim 13, Patent No.: US 12,070,875 B2, as applied to claim 1, does not explicitly disclose
the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio of at least 400.
However, Swoboda et al., at least implicitly, teaches the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio of at least 400 (Swoboda et al. – Par. 0167 together with Par. 0602). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Swoboda et al. to adapt the SiC wafer, wherein the SiC wafer of Patent No.: US 12,070,875 B2 comprises a diameter to thickness ratio of at least 400 in order to make sure that the wafer sag during epitaxial growth is countered by the positive bow of the wafer so that growth happens on a flat surface
Regarding Claim 14, Patent No.: US 12,070,875 B2, as applied to claim 1, does not explicitly disclose
the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio in a range of about 250 to 1020.
However, Swoboda et al., at least implicitly, teaches the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio in a range of about 250 to 1020 (Swoboda et al. – Par. 0167 together with Par. 0602). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Swoboda et al. to adapt the SiC wafer, wherein the SiC wafer of Patent No.: US 12,070,875 B2 comprises a diameter to thickness ratio in a range of about 250 to 1020 in order to make sure that the wafer sag during epitaxial growth is countered by the positive bow of the wafer so that growth happens on a flat surface
Regarding Claim 15, Patent No.: US 12,070,875 B2, as applied to claim 1, does not explicitly disclose
the SiC wafer, wherein the wafer is an n-type conductive SiC wafer (claims of this patent is silent regarding the conductivity of the SiC wafer, although it is understood that it is either n- or p-type conductive or semi-insulating or unintentionally doped).
However, Swoboda et al., at least implicitly, teaches the SiC wafer, wherein the wafer is an n-type conductive SiC wafer (Swoboda et al. – Par. 0134, 0419, & 0564). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Swoboda et al. to adapt the SiC wafer, wherein the wafer of Patent No.: US 12,070,875 B2 is an n-type conductive SiC wafer as such wafers are commonly used for many applications.
Regarding Claim 16, Patent No.: US 12,070,875 B2, as applied to claim 1, does not explicitly disclose
the SiC wafer, wherein the wafer is a semi-insulating SiC wafer (claims of this patent is silent regarding the conductivity of the SiC wafer, although it is understood that it is either n- or p-type conductive or semi-insulating or unintentionally doped).
However, Swoboda et al., at least implicitly, teaches the SiC wafer, wherein the wafer is a semi-insulating SiC wafer (Swoboda et al. – Par. 0134, 0419, & 0564). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Swoboda et al. to adapt the SiC wafer, wherein the wafer of Patent No.: US 12,070,875 B2 is a semi-insulating SiC wafer as such wafers are commonly used for many applications.
Regarding Claim 17, Patent No.: US 12,070,875 B2, as applied to claim 1, does not explicitly disclose
the SiC wafer, wherein the SiC wafer is an unintentionally doped SiC wafer (claims of this patent is silent regarding the conductivity of the SiC wafer, although it is understood that it is either n- or p-type conductive or semi-insulating or unintentionally doped).
However, Swoboda et al., at least implicitly, teaches the SiC wafer, wherein the SiC wafer is an unintentionally doped SiC wafer (Swoboda et al. – Par. 0134, 0419, & 0564). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Swoboda et al. to adapt the SiC wafer, wherein the wafer of Patent No.: US 12,070,875 B2 is an unintentionally doped SiC wafer as such wafers are commonly used for many applications.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 and 11-17 are rejected under 35 U.S.C. 103 as obvious over Swoboda et al. (Pub. No.: US 2020/0388538 A1) in view of Leonard et al. (Patent No.: US 2008/0008641 A1).
Regarding Claim 1, Swoboda et al. discloses a silicon carbide (SiC) wafer comprising: a silicon face and a carbon face (Par. 0362 - implied); a diameter of at least 200 millimeters (mm) (Par. 0055); and a relaxed positive bow from the silicon face (Par. 0527-0538; Figs. 29a-31a). Swoboda et al. does not explicitly disclose wherein a surface of the SiC wafer is not parallel to a crystallographic c-plane associated with the SiC wafer.
However, Leonard et al. discloses
wherein a surface of the SiC wafer is not parallel to a crystallographic c-plane associated with the SiC wafer (Par. 0011-0012 & 0019-0020 – this prior art teaches “Off-axis growth may reduce random nucleation and thus encourage silicon carbide epilayers to grow with greater lattice accuracy. This is understood as resulting from the greater number of "steps" that are exposed on an off-axis face in comparison to an on-axis face”).
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Leonard et al. to adapt a silicon carbide (SiC) wafer wherein a surface of the SiC wafer of Swoboda et al. is not parallel to a crystallographic c-plane associated with the SiC wafer in order to grow better quality wafer by reducing random nucleation.
Regarding Claim 2, modified Swoboda et al., as applied to claim 1, at least implicitly, discloses the silicon carbide wafer, wherein a surface of the SiC wafer is misaligned with a crystallographic c-plane by an oblique angle relative to the crystallographic c-plane (Leonard et al. – Par. 0011-0012 & 0019-0020).
Regarding Claim 3, modified Swoboda et al., as applied to claim 2, at least implicitly, discloses the silicon carbide wafer, wherein the oblique angle is in a range from 1 to 10 degrees (Leonard et al. – Par. 0011-0012 & 0019-0020).
Regarding Claim 4, modified Swoboda et al., as applied to claim 2, at least implicitly, discloses the silicon carbide wafer, wherein the oblique angle is in a range from 2 to 6 degrees (Leonard et al. – Par. 0011-0012 & 0019-0020).
Regarding Claim 5, modified Swoboda et al., as applied to claim 2, at least implicitly, discloses the silicon carbide wafer, wherein the oblique angle is 4 degrees (Leonard et al. – Par. 0011-0012 & 0019-0020).
Regarding Claim 6, modified Swoboda et al., as applied to claim 1, at least implicitly, discloses the SiC wafer, wherein the diameter is in a range from 200 mm to 205 mm (Swoboda et al. – Par. 0602).
Regarding Claim 11, modified Swoboda et al., as applied to claim 1, at least implicitly, discloses the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio of at least 250 (Swoboda et al. – Par. 0167 together with Par. 0602).
Regarding Claim 12, modified Swoboda et al., as applied to claim 1, at least implicitly, discloses the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio of at least 350 (Swoboda et al. – Par. 0167 together with Par. 0602).
Regarding Claim 13, modified Swoboda et al., as applied to claim 1, at least implicitly, discloses the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio of at least 400 (Swoboda et al. – Par. 0167 together with Par. 0602).
Regarding Claim 14, modified Swoboda et al., as applied to claim 1, at least implicitly, discloses the SiC wafer, wherein the SiC wafer comprises a diameter to thickness ratio in a range of about 250 to 1020 (Swoboda et al. – Par. 0167 together with Par. 0602).
Regarding Claim 15, modified Swoboda et al., as applied to claim 1, discloses
the SiC wafer, wherein the wafer is an n-type conductive SiC wafer (Swoboda et al. – Par. 0134, 0419, & 0564).
Regarding Claim 16, modified Swoboda et al., as applied to claim 1, discloses
the SiC wafer, wherein the wafer is a semi-insulating SiC wafer (Swoboda et al. – Fig. 37b).
Regarding Claim 17, modified Swoboda et al., as applied to claim 1, discloses
the SiC wafer, wherein the SiC wafer is an unintentionally doped SiC wafer (Swoboda et al. – Par. 0362).
Claims 7-10 are rejected under 35 U.S.C. 103 as obvious over Swoboda et al. (Pub. No.: US 2020/0388538 A1) and Leonard et al. (Patent No.: US 2008/0008641 A1), as applied to claim 1.
Regarding Claim 7, Swoboda et al., as applied to claim 1, discloses
the SiC wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to a desired value (Par. 0538-0541; Figs. 31a-31c – the wafer 4 has a certain relaxed positive bow; the extent of the curvature depends on what is desired in the long run; for example, if a metal or semiconductor layer 50 is to be deposited on the wafer 4 and a flat planar surface is desired for the multicomponent arrangement 39, the positive bow of the wafer 4 has to be decided based on the particulars of the metal/semiconductor 50 involved and the particulars of the processes involved). Swoboda et al. does not explicitly disclose
the SiC wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to 50 µm.
In a nutshell, Swoboda et al. discloses the claimed invention except for the SiC wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to 50 µm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the SiC wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to 50 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 8, Swoboda et al., as applied to claim 1, discloses
the SiC wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to a desired value (Par. 0538-0541; Figs. 31a-31c – the wafer 4 generated has a certain relaxed positive bow; the extent of the curvature depends on what is desired in the long one; for example, if a metal or semiconductor layer 50 is to be deposited on the wafer 4 and a flat planar surface is desired the multicomponent arrangement 39, the positive bow of the wafer 4 has to be decided based on the particulars of the metal/semiconductor 50 involved and the particulars of the processes involved). Swoboda et al. does not explicitly disclose
the SiC wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to 15 µm.
In a nutshell, Swoboda et al. discloses the claimed invention except for the SiC wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to 15 µm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the SiC wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to 15 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 9, Swoboda et al., as applied to claim 1, discloses
the SiC wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to a desired value (Par. 0538-0541; Figs. 31a-31c – the wafer 4 generated has a certain relaxed positive bow; the extent of the curvature depends on what is desired in the long one; for example, if a metal or semiconductor layer 50 is to be deposited on the wafer 4 and a flat planar surface is desired the multicomponent arrangement 39, the positive bow of the wafer 4 has to be decided based on the particulars of the metal/semiconductor 50 involved and the particulars of the processes involved). Swoboda et al. does not explicitly disclose
the SiC wafer, wherein the relaxed positive bow is in a range including 30 µm to 50 µm.
In a nutshell, Swoboda et al. discloses the claimed invention except for the SiC wafer, wherein the relaxed positive bow is in a range including 30 µm to 50 µm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the SiC wafer, wherein the relaxed positive bow is in a range including 30 µm to 50 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 10, Swoboda et al., as applied to claim 1, discloses
the SiC wafer, wherein the relaxed positive bow is in a range from greater than 0 µm to a desired value (Par. 0538-0541; Figs. 31a-31c – the wafer 4 generated has a certain relaxed positive bow; the extent of the curvature depends on what is desired in the long one; for example, if a metal or semiconductor layer 50 is to be deposited on the wafer 4 and a flat planar surface is desired the multicomponent arrangement 39, the positive bow of the wafer 4 has to be decided based on the particulars of the metal/semiconductor 50 involved and the particulars of the processes involved). Swoboda et al. does not explicitly disclose
the SiC wafer, wherein the relaxed positive bow is in a range including 8 µm to 16 µm.
In a nutshell, Swoboda et al. discloses the claimed invention except for the SiC wafer, wherein the relaxed positive bow is in a range including 8 µm to 16 µm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the SiC wafer, wherein the relaxed positive bow is in a range including 8 µm to 16 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kido et al. (Patent No.: US 11781244 B2) – This prior art teaches a silicon carbide (SiC) wafer (100) comprising: a silicon face and a carbon face; a diameter of at least Fig. 1).
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08/06/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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