DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/775,939 filed July 17, 2024. Claims 1-20 are currently pending and have been considered below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 & 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (Pre-Grant Publication 2022/0068957) in view of Nosho (Pre-Grant Publication 2018/0342455).
Regarding claim 12 & 14-15, Yeh discloses a memory device comprising:
a second transistor (Fig. 1, 161) formed in a second area of the substrate (not shown; Paragraph [0049]).
a plurality of interconnect structures (163) over the second transistors in a vertical direction;
an etch stop layer (126; Paragraph [0056]) disposed over the plurality of interconnect structures in the vertical direction;
a plurality of memory strings (Fig. 4, 122) disposed above the etch stop layer, each of the plurality of memory strings extending in the vertical direction;
a second conductive structure (Fig. 2b, 114) extending in the vertical direction to penetrate through the etch stop layer to be electrically coupled to the second transistor.
Yeh further disclose the second transistor (161) can serve as a source line switch/driver or a bitline switch/driver circuit (Paragraph [0045 & 0046]).
Yeh does not disclose a first transistor formed in a first area of a substrate, interconnect structures over the first transistor, and a first conductive structure electrically coupled to the first transistor. However Nosho discloses a memory device comprising:
A first transistor (See Fig. Below) formed on a first area of a substrate (9).
A interconnect structure (788) disposed over the first transistor in a vertical direction.
A first conductive structure (488) extending in the vertical direction to penetrate through a etch stop layer (6; Paragraph [0115]) to be electrically coupled to the first transistor.
The first can operative serve as a circuit such as a power circuit (Paragraph [0043]).
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It would have been obvious to those having ordinary skill in the art at the time of invention to form the transistor in the first area having a first conductive structure electrically coupled to the transistor because the transistor in the first area can serve as peripheral circuit such as a power supply/distribution to assist operating the array of memory devices (Paragraph [0043]).
Regarding claim 16, Yeh further discloses:
a third transistor (Fig. 1, 192) interposed between the first transistor and the second transistor in the lateral direction; and
a third conductive structure (Fig. 2e, 114) extending in the vertical direction to penetrate through the etch stop layer to be electrically coupled to the third transistor.
Regarding claim 17, Yeh further discloses:
A interface portion/staircase portions (101 & 101a-101c) disposed next to the memory strings (122) including a plurality of word lines/gate structures/conductive layer (106) (Paragraph [0022]) extending in the lateral direction, wherein the third conductive structure (Fig. 2e, 114) is electrically coupled to the word lines.
Allowable Subject Matter
Claims 1-11 & 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance: Claim 1 is allowed because none of the prior art either alone or in combination discloses a memory device comprising: a plurality of memory strings disposed above an etch stop layer, each of the plurality of memory strings extending along a vertical direction; a first conductive structure extending along the vertical direction to penetrate through the etch stop layer to electrically couple to a first transistor disposed below the plurality of memory strings; and a second conductive structure extending along the vertical direction to penetrate through the etch stop layer to electrically couple to a second transistor disposed below the plurality of memory strings; wherein the first conductive structure is separated apart from the memory strings along a lateral direction, and the second conductive structure is disposed inside one of the memory strings. Claims 2-11 are also allowed based on their dependency from claim 1.
Claim 18 is allowed because none of the prior art either alone or in combination discloses a memory device comprising: a plurality of memory strings disposed above the etch stop layer, each of the plurality of memory strings extending in the vertical direction; a first conductive structure extending in the vertical direction to penetrate through the etch stop layer to be electrically coupled to the first transistor; and a second conductive structure extending in the vertical direction to penetrate through the etch stop layer to be electrically coupled to the second transistor; wherein the first conductive structure is separated apart from the memory strings along the lateral direction, and the second conductive structure is disposed inside one of the memory strings, in combination with the other limitations of claim 1. Claims 19-20 are also allowed based on their dependency from claim 18.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 13 is considered allowable because none of the prior art either alone or in combination discloses the first conductive structure is separated apart from the memory strings along the lateral direction, and the second conductive structure is disposed inside one of the memory strings.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kidoh (Pre-Grant Publication 2010/0320526) discloses a non-volatile semiconductor memory device comprising a peripheral region circuitry, a word line region and memory cell region.
Jiang (Pre-Grant Publication 2024/0081078) disclose a memory device comprising a staircase stacked structure comprising a channel layer and memory layer penetrating the stack.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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