DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/17/2024 and 05/06/2025 were filed before the first action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 12,119,401. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 12 of U.S. Patent No. 12,119,401 recites all the limitations in claim 1 of the instant application.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 12,119,401. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 15 of U.S. Patent No. 12,119,401 recites all the limitations in claim 8 of the instant application.
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 12,119,401. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 15 of U.S. Patent No. 12,119,401 recites all the limitations in claim 11 of the instant application. Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. 12,119,401. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 16 of U.S. Patent No. 12,119,401 recites all the limitations in claim 12 of the instant application.
Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 12,119,401. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 12 of U.S. Patent No. 12,119,401 recites all the limitations in claim 14 of the instant application.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 12,119,401. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 12 of U.S. Patent No. 12,119,401 recites all the limitations in claim 15 of the instant application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 6 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (2019/0097006).
Re claim 1, Li teaches a semiconductor device (Figs. 1-9) comprising: a fin (204) extending from a substrate (200); a gate stack (256) over and along sidewalls of the fin (Fig. 1); a source/drain region (220) in the fin (204) adjacent to the gate stack (256), the source/drain region (220) comprising: a first epitaxial layer (220-1) on the fin (204), the first epitaxial layer (220-1) having a first dopant concentration of boron [28]; and a second epitaxial layer (220-2) on the first epitaxial layer (220-1), the second epitaxial layer (220-2) having a second dopant concentration of boron [28], wherein the second dopant concentration is in a range from 1021 cm-3 to 1022 cm-3 and is from two to ten times greater than the first dopant concentration [28]. Re claim 3, Li teaches the semiconductor device of claim 1, further comprising a gate spacer (218) along a sidewall of the gate stack (256), wherein both the first (220-1) and second (220-2) epitaxial layers physically contact the gate spacer (218).
Re claim 4, Li teaches the semiconductor device of claim 1, wherein the second epitaxial layer (220-2) has a flat top surface (H1, Fig. 2A).
Re claim 6, Li teaches the semiconductor device of claim 1, wherein the first (220-1) and second (220-2) epitaxial layers comprise silicon-germanium [26].
Re claim 7, Li teaches the semiconductor device of claim 6, wherein the second epitaxial layer (220-2) has a higher atomic percentage of germanium [37] than the first epitaxial layer (220-1).
Claim(s) 8 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (2019/0097006).
Re claim 8, Li teaches a method (Fig. 1-9) comprising: forming a dummy gate (215) over and along sidewalls of a fin (204) extending from a substrate (200); forming a gate spacer (218) along a sidewall of the dummy gate (215); etching a recess [26] in the fin (204) adjacent to the gate spacer (218); epitaxially growing a first layer (220-1) in the recess [26] using a first set of growth conditions [27], the first layer having a first dopant concentration of boron [28]; epitaxially growing a second layer (220-2) on the first layer (220-1) using a second set of growth conditions [27], the second layer having a second dopant concentration of boron [28], wherein the second set of growth conditions includes a higher flow rate of a boron-containing gas compared to the first set of growth conditions [26-27], the second dopant concentration being from two to ten times greater than the first dopant concentration [28]; and replacing the dummy gate (215) with an active gate stack (256).
Re claim 12, Li teaches the method of claim 8, wherein the second layer is grown for a shorter duration than the first layer [26-28].
Re claim 13, Li teaches the method of claim 8, wherein the second layer is grown to a thickness between 5 nm and 30 nm [28].
Re claim 14, Li teaches the method of claim 8, wherein the first (220-1) and second (220-2) layers comprise silicon-germanium [26].
Claim(s) 15-16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (2019/0097006).
Re claim 15, Li teaches a semiconductor device comprising: a plurality of fins (204) extending from a substrate (200); a plurality of gate stacks (256), each gate stack (256) disposed over and along sidewalls of a respective fin (204); source/drain regions (220) in the fins adjacent to the gate stacks (256), each source/drain region comprising: a first epitaxial portion (220-1) having a first dopant concentration of boron [28]; and a second epitaxial portion (220-2) on the first epitaxial portion (220-1), the second epitaxial portion (220-2) having a second dopant concentration of boron [28], wherein for each source/drain region the second dopant concentration is in a range from 1021 cm-3 to 1022 cm-3, and the second dopant concentration is from two to ten times greater than the first dopant concentration [28].
Re claim 16, Li teaches the semiconductor device of claim 15, wherein the second epitaxial portion (220-2) has a thickness in a range from 5 nm to 30 nm [28].
Re claim 18, Li teaches the semiconductor device of claim 15, wherein the first epitaxial portions (220-1) of adjacent source/drain regions (220) are separated from each other (Fig. 9).
Re claim 19, Li teaches the semiconductor device of claim 15, further comprising gate spacers (218) along sidewalls of the gate stacks (256), wherein the second epitaxial portions (220-1) physically contact the gate spacers (218).
Re claim 20, Li teaches the semiconductor device of claim 15, wherein the first (220-1) and second (220-2) epitaxial portions comprise silicon-germanium [26], and the second epitaxial portions (220-2) have a higher atomic percentage of germanium than the first epitaxial portions [37].
Allowable Subject Matter
Claims 2, 5, 9-11 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 2, Li teaches the semiconductor device of claim 1, yet remains explicitly silent to wherein the first epitaxial layer has a convex top surface and the second epitaxial layer conformally covers the convex top surface of the first epitaxial layer.
Re claim 5, Li teaches the semiconductor device of claim 1, further comprising: an etch stop layer (221) over the source/drain region (220); an interlayer dielectric (222) over the etch stop layer (221); and a conductive contact (244) extending through the interlayer dielectric (222) and the etch stop layer (221).
Li does not explicitly teach the conductive contact to physically contact the second epitaxial layer.
Re claim 9, Li teaches the method of claim 8, yet remains explicitly silent to wherein the first set of growth conditions comprises a temperature between 580ºC and 630ºC, a pressure between 17 torr and 25 torr, a flow rate of dichlorosilane between 30 sccm and 60 sccm, a flow rate of germane between 400 sccm and 800 sccm, and a flow rate of diborane between 40 sccm and 150 sccm.
Claim 10 is objected to for at least depending from objected claim 9. Re claim 11, Li teaches the method of claim 8, further comprising: forming an etch stop layer (221) over the second layer (220-2); forming an interlayer dielectric (222) over the etch stop layer (221); and forming a conductive contact (244) through the interlayer dielectric (222) and the etch stop layer (221).
Li does not explicitly teach the conductive contact to physically contact the second layer. Re claim 17, Li teaches the semiconductor device of claim 15, yet remains explicitly silent to further comprising conductive contacts physically contacting the second epitaxial portions of the source/drain regions.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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