DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song et al. (US 2018/0190829) (hereafter Song).
Regarding claim 18, Song discloses a semiconductor device, comprising:
a plurality of channel members 120 (Fig. 2, paragraph 0022) vertically stacked;
a source/drain feature 105 (Fig. 2, paragraph 0025) abutting the channel members 120 (Fig. 2);
a gate structure 130 (Fig. 2, paragraph 0025) engaging the channel members 120 (Fig. 2);
a first isolation structure (first 108, first 142, second 142 from the left corner of Fig. 2) including a first air gap (first 108 from the left corner of Fig. 2, paragraph 0025); and
a second isolation structure (second 108, third 142, fourth 142 from the left corner of Fig. 2) including a second air gap (second 108 from the left corner of Fig. 2, paragraph 0025), wherein the first (first 108 from the left corner of Fig. 2) and second air gaps (second 108 from the left corner of Fig. 2) sandwich the gate structure 130 (Fig. 2) laterally therebetween.
Regarding claim 19, Song further discloses the semiconductor device of claim 18, wherein the first (first 108 from the left corner of Fig. 3) and second air gaps (second 108 from the left corner of Fig. 3) sandwich the source/drain feature 105 (Fig. 3) laterally therebetween.
Regarding claim 20, Song further discloses the semiconductor device of claim 18, wherein the channel members 120 (Fig. 2) extend laterally from a sidewall of the first isolation structure (first 108, first 142, second 142 from the left corner of Fig. 2), and wherein the gate structure 130 (Fig. 2) separates the channel members 120 (Fig. 2) from the second isolation structure (second 108, third 142, fourth 142 from the left corner of Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 2018/0190829) (hereafter Song), in view of Yokoyama et al. (US 2015/0060967) (hereafter Yokoyama).
Regarding claim 11, Song discloses a semiconductor device, comprising:
a plurality of channel members 120 (Fig. 2, paragraph 0022) vertically stacked;
a source/drain feature 105 (Fig. 2, paragraph 0025) abutting the channel members 120 (Fig. 2);
a gate structure (110 and 130 in Fig. 2, paragraph 0025) engaging the channel members 120 (Fig. 2); and
an isolation structure (108, 142, 140, and 130 in Fig. 2).
Song does not disclose a first metal interconnect layer disposed at a frontside of the semiconductor device;
a second metal interconnect layer disposed at a backside of the semiconductor device;
a backside source/drain contact electrically coupling the source/drain feature to the second metal interconnect layer; and
an isolation structure stacked vertically between the first and second interconnect layers, wherein the isolation structure interfaces a sidewall of the backside source/drain contact, a sidewall of the source/drain feature, and a sidewall of the gate structure.
Yokoyama discloses a first metal interconnect layer 40A (Fig. 1A, paragraph 0125) disposed at a frontside (bottom side in Fig. 1A) of the semiconductor device;
a second metal interconnect layer 31 (Fig. 1A, paragraph 0128) disposed at a backside (top side in Fig. 1A) of the semiconductor device;
a backside source/drain contact (P1 in Fig. 1A, paragraph 0128) electrically coupling the source/drain feature 22D (Fig. 1A, paragraph 0159) to the second metal interconnect layer 31 (Fig. 1A); and
an isolation structure (24, 26, and 11 in Fig. 1A) stacked vertically between the first 40A (Fig. 1A) and second interconnect layers 31 (Fig. 1A), wherein the isolation structure (24, 26, and 11 in Fig. 1A) interfaces a sidewall of the backside source/drain contact (P1 in Fig. 1A), a sidewall of the source/drain feature 22D (Fig. 1A), and a sidewall of the gate structure (23 and 21 in Fig. 1A, paragraph 0122).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Song to form a first metal interconnect layer disposed at a frontside of the semiconductor device; a second metal interconnect layer disposed at a backside of the semiconductor device; a backside source/drain contact electrically coupling the source/drain feature to the second metal interconnect layer; and an isolation structure stacked vertically between the first and second interconnect layers, wherein the isolation structure interfaces a sidewall of the backside source/drain contact, a sidewall of the source/drain feature, and a sidewall of the gate structure, as taught by Yokoyama, since contact plugs P1 and P2 (Yokoyama, Fig. 1A, paragraph 0120) so extending as to pass through a portion where the insulating film 63 (Yokoyama, Fig. 1A, paragraph 0120) and the element isolation layer 11 (Yokoyama, Fig. 1A, paragraph 0120) are connected to each other are provided to the isolation region R2 (Yokoyama, Fig. 1A, paragraph 0120). In addition, since peripheries of the contact plugs P1 and P2 (Yokoyama, Fig. 1A, paragraph 0120) are covered with a part of the insulating film 63 (Yokoyama, Fig. 1A, paragraph 0120), and are electrically isolated from the semiconductor substrate 10 (Yokoyama, Fig. 1A, paragraph 0120).
Regarding claim 12, Song further discloses the semiconductor device of claim 11, wherein the isolation structure (108, 142, 140, and 130 in Fig. 2) includes an air gap 108 (Fig. 2, paragraph 0025) trapped therein.
Regarding claim 13, Song further discloses the semiconductor device of claim 12, wherein a top portion of the air gap 108 (Fig. 2) is above a bottom surface of the gate structure (110 and 130 in Fig. 2).
Regarding claim 14, Song further discloses the semiconductor device of claim 12, wherein a bottom portion of the air gap 108 (Fig. 2) is below a bottom surface of the gate structure (110 and 130 in Fig. 2).
Regarding claim 15, Song in view of Yokoyama discloses the semiconductor device of claim 11, however Song does not disclose a metal cap layer disposed on a top surface of the gate structure, wherein the metal cap layer covers a top surface of the isolation structure.
Yokoyama discloses a metal cap layer (28A and WL in Fig. 1A, paragraph 0124) disposed on a top surface of the gate structure (23 and 21 in Fig. 1A, paragraph 0122), wherein the metal cap layer (28A and WL in Fig. 1A covers a top surface of the isolation structure (24, 26, and 11 in Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Song to form a metal cap layer disposed on a top surface of the gate structure, wherein the metal cap layer covers a top surface of the isolation structure, as taught by Yokoyama, since a metal cap layer (Yokoyama, 28A and WL in Fig. 1A, paragraph 0124) provides electrical connection between the gate structure and the other devices.
Regarding claim 16, Song further discloses the semiconductor device of claim 11, wherein the gate structure (110 and 130 in Fig. 2) includes a gate dielectric layer 110 (Fig. 2, paragraph 0023) and a gate electrode layer 130 (Fig. 2, paragraph 0023), and wherein the isolation structure (108, 142, 140, and 130 in Fig. 2) interfaces the gate dielectric layer 110 (Fig. 2).
Regarding claim 17, Song further discloses the semiconductor device of claim 11, wherein the gate structure (110 and 130 in Fig. 2) includes a gate dielectric layer 110 (Fig. 2, paragraph 0023) and a gate electrode layer 130 (Fig. 2, paragraph 0023), and wherein the isolation structure (108, 142, 140, and 130 in Fig. 2) interfaces the gate electrode layer 130 (Fig. 2).
Allowable Subject Matter
Claims 1-10 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Song et al. (US 2018/0190829), discloses a first gate structure (first 110 and first 130 from the left corner of Fig. 2, paragraph 0023) engaging the first channel members (first 120 from the left corner of Fig. 2); a second gate structure (second 110 and second 130 from the left corner of Fig. 2, paragraph 0023) engaging the second channel members (second 120 from the left corner of Fig. 2); and wherein the isolation structure (108, 142, 140, and 130 in Fig. 2) includes an air gap 108 (Fig. 2, paragraph 0025) stacked laterally between the first (first 110 and first 130 from the left corner of Fig. 2) and second gate structures (second 110 and second 130 from the left corner of Fig. 2) but fails to disclose a first metal interconnect layer disposed at a frontside of the semiconductor device; a second metal interconnect layer disposed at a backside of the semiconductor device, wherein the first and second gate structures are stacked vertically between the first and second metal interconnect layers; and an isolation structure stacked vertically between the first and second metal interconnect layers. Additionally, the prior art does not teach or suggest a semiconductor device, comprising: an isolation structure stacked vertically between the first and second metal interconnect layers, wherein the isolation structure includes an air gap stacked laterally between the first and second gate structures in combination with other elements of claim 1.
A closest prior art, Song et al. (US 2018/0190829), discloses a semiconductor device, comprising: a plurality of first channel members (first 120 from the left corner of Fig. 2, paragraph 0022) vertically stacked; a plurality of second channel members (second 120 from the left corner of Fig. 2, paragraph 0022) vertically stacked; a first source/drain feature (first 105 from the left corner of Fig. 2) abutting the first channel members (first 120 from the left corner of Fig. 2); a second source/drain feature (second 105 from the left corner of Fig. 2) abutting the second channel members (second 120 from the left corner of Fig. 2); a first gate structure (first 110 and first 130 from the left corner of Fig. 2, paragraph 0023) engaging the first channel members (first 120 from the left corner of Fig. 2); a second gate structure (second 110 and second 130 from the left corner of Fig. 2, paragraph 0023) engaging the second channel members (second 120 from the left corner of Fig. 2); and wherein the isolation structure (108, 142, 140, and 130 in Fig. 2) includes an air gap 108 (Fig. 2, paragraph 0025) stacked laterally between the first (first 110 and first 130 from the left corner of Fig. 2) and second gate structures (second 110 and second 130 from the left corner of Fig. 2) but fails to teach a first metal interconnect layer disposed at a frontside of the semiconductor device; a second metal interconnect layer disposed at a backside of the semiconductor device, wherein the first and second gate structures are stacked vertically between the first and second metal interconnect layers; and an isolation structure stacked vertically between the first and second metal interconnect layers as the context of claim 1. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 2-10 depend on claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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