DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of provisional application 62/928,671 submitted on 10/31/2019 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) filed on August 19, 2022 and IDS filed on November 10, 2022 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 6-8, 13, and 19-20 are objected to because of the following informalities:
In claim 6, line 2, “doped implant region is in a range of 50% concentration by volume” should read-- dopant implant region is
In claim 7, line 1, “the doped implant region” should read --the dopant implant region-- (emphasis added).
In claim 8, line 1, “the doped implant region” should read --the dopant implant region-- and line 2, “a topmost surface of interlayer dielectric layer” should read --a topmost surface of the interlayer dielectric layer-- (emphasis added).
In claim 13, line 3, “has a third equal to the second width” should read --has a third width equal to the second width-- (emphasis added).
In claim 19, line 4, “from the group consisting a metal oxide” should read --from the group consisting of a metal oxide-- and lines 9 and 11-13, “the interlayer dielectric layer” should read --the porous interlayer dielectric layer-- (emphasis added).
In claim 20, lines 2-3, “the interlayer dielectric layer” should read --the porous interlayer dielectric layer-- and line 3, “to topmost surface of the etch stop layer” should read --to a topmost surface of the etch stop layer-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation “the doped implant region has a concentration of dopants of between about 1E15 and about 5E15” in lines 1-2. However, the claim does not specify a unit of measurement for the recited concentration values. Although the Specification similarly refers to dopant concentrations between about 1E15 and about 5E15, the Specification does not identify a corresponding unit of measurement. Therefore, it is unclear whether the recited values represent a volumetric dopant concentration, an implantation dose, or another concentration measurement, and the scope of the claimed dopant concentration cannot be determined.
For best understanding and examination purpose, the claim will be best considered based on drawings, disclosure, and/or any applicable prior arts.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-11 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Apelgren et al. (US 2003/0013296; hereinafter ‘Apelgren’).
Regarding claim 9, Apelgren teaches a semiconductor device (FIG. 19, [0018, 0022]), comprising:
a metallization layer (1125, [0024, 0039]) over a semiconductor substrate (1100, [0039]);
an etch stop layer (1110, [0040]) over the metallization layer (1125);
an interlayer dielectric layer (1120, [0040]) over the etch stop layer (1110);
a hole (a hole including 1220 and 1230, FIG. 12, [0044]; hereinafter ‘H’) extending through the interlayer dielectric layer (1120), the hole being lined with a doped region (a dopant implant region including 1420 and 1430, Figure 14, [0043]; hereinafter ‘DR’) of the interlayer dielectric layer (H being lined with 1420 of 1120); and
a metal plug (1640, [0050]) filling the hole (1640 filing H).
Regarding claim 10, Apelgren teaches the semiconductor device of claim 9, further comprising a barrier layer (a barrier layer including 1725A and 1725B, FIG. 17, [0050]; hereinafter ‘1725’) interjacent the metal plug and the doped region of the interlayer dielectric layer (1725 interjacent 1640 and DR, FIGS. 17 and 19).
Regarding claim 11, Apelgren teaches the semiconductor device of claim 9, wherein the doped region extends along a topmost surface of the interlayer dielectric layer (1430 of DR extends along a topmost surface of 1120, FIG. 19).
Regarding claim 14, Apelgren teaches the semiconductor device of claim 9, wherein the doped region extends continuously from a top of the interlayer dielectric layer to the bottom of the interlayer dielectric layer (DR extends continuously from a top of 1120 to the bottom of 1120, FIG. 19).
Regarding claim 15, Apelgren teaches the semiconductor device of claim 14, wherein the doped region has a constant thickness from the top of the interlayer dielectric layer to the bottom of the interlayer dielectric layer (DR has a constant thickness form the top of 1120 to the bottom of 1120, FIG. 19).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Apelgren (US 2003/0013296) in view of Chen et al. (US 2016/0027729; hereinafter ‘Chen’).
Regarding claim 1, Apelgren teaches a semiconductor device (FIG. 19, [0018, 0022]), comprising:
a metallization layer (1125, [0024, 0039]) over a semiconductor substrate (1100, [0039]);
an etch stop layer (1110, [0040]) over the metallization layer (1125);
an interlayer dielectric layer (1120, [0040]) over the etch stop layer (1110);
a metal plug (a metal plug including 1640, at least one inner barrier metal sublayer of multilayer barrier structure 1725A, and 1725B, FIGS. 17 and 19, [0050-0051]; hereinafter ‘MP’)
extending through the interlayer dielectric layer (1120) and through the etch stop layer (1110) and
contacting the metallization layer (1125), and
a dopant implant region (a dopant implant region including 1420 and 1430, FIG. 14, [0043]; hereinafter ‘DIR’) within the interlayer dielectric layer (1420 of DIR within 1120) and surrounding sidewalls of the metal plug (DIR surrounding sidewalls of MP, FIG. 19).
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Apelgren does not teach the semiconductor device wherein the metal plug has a first width at the top of the interlayer dielectric layer, has a second width less than the first width at the bottom of the interlayer dielectric layer, and has a third width greater than the second width at the bottom of the etch stop layer.
Chen teaches a semiconductor device (FIG. 8, [0025]) comprising
a metal plug (160, [0045]) wherein the metal plug (160)
has a first width at the top of the interlayer dielectric layer (a first width W1 at the top of 140, [0044], see the annotated in FIG. 8),
has a second width less than the first width at the bottom of the interlayer dielectric layer (a second width W2 less than W1 at the bottom of 140, see the annotated in FIG. 8), and
has a third width greater than the second width at the bottom of the etch stop layer (a third width W3 greater than W2 at the bottom of 130, see the annotated in FIG. 8).
As taught by Chen, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren to obtain and achieve the semiconductor device comprising a metal plug, wherein the metal plug has a first width at the top of the interlayer dielectric layer, has a second width less than the first width at the bottom of the interlayer dielectric layer, and has a third width greater than the second width at the bottom of the etch stop layer as claimed, because the widened upper portion provides access for deposition and filling of the metal plug, the narrowed intermediate portion permits the lower portion to be selectively enlarged without enlarging the metal plug throughout the interlayer dielectric layer, and the widened lower portion increases the contact area with the underlying metallization layer, thereby improving adhesion and electrical connectivity without increasing bridging between adjacent metal plugs, [0030-0035, 0043-0046].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chen in combination with Apelgren due to the above reason.
Regarding claim 2, Apelgren in view of Chen teaches the semiconductor device of claim 1, further comprising a barrier layer (Apelgren: an outermost barrier metal sublayer of multilayer barrier structure 1725A, FIG. 17, [0050-0051]; hereinafter ‘1725AOUT’) interjacent the metal plug and the dopant implant region (1725 interjacent MP and DIR, FIGS. 17 and 19).
Regarding claim 8, Apelgren in view of Chen teaches the semiconductor device of claim 1, wherein the doped implant region extends along a topmost surface of interlayer dielectric layer (Apelgren: 1430 of DIR extends along a topmost surface of 1120, FIG. 19).
Regarding claim 12, Apelgren teaches the semiconductor device of claim 9, but does not teach the semiconductor device wherein the metal plug has a first width at the top of the interlayer dielectric layer, has a second width less than the first width at the bottom of the interlayer dielectric layer, and has a third width greater than the second width at the bottom of the etch stop layer.
Chen teaches a semiconductor device (FIG. 8, [0025]) wherein
the metal plug (160, [0045]) has a first width at the top of the interlayer dielectric layer (a first width W1 at the top of 140, [0044], see the annotated in FIG. 8),
has a second width less than the first width at the bottom of the interlayer dielectric layer (a second width W2 less than W1 at the bottom of 140, see the annotated in FIG. 8), and
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has a third width greater than the second width at the bottom of the etch stop layer (a third width W3 greater than W2 at the bottom of 130, see the annotated in FIG. 8).
As taught by Chen, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren to obtain and achieve the semiconductor device wherein the metal plug has a first width at the top of the interlayer dielectric layer, has a second width less than the first width at the bottom of the interlayer dielectric layer, and has a third width greater than the second width at the bottom of the etch stop layer as claimed, because the widened upper portion provides access for deposition and filling of the metal plug, the narrowed intermediate portion permits the lower portion to be selectively enlarged without enlarging the metal plug throughout the interlayer dielectric layer, and the widened lower portion increases the contact area with the underlying metallization layer, thereby improving adhesion and electrical connectivity without increasing bridging between adjacent metal plugs, [0030-0035, 0043-0046].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chen in combination with Apelgren due to the above reason.
Claims 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Apelgren (US 20030013296) in view of Chen (US 2016/0027729), and further in view of Wann et al. (US 2013/0221491; hereinafter ‘Wann’).
Regarding claim 3, Apelgren in view of Chen teaches the semiconductor device of claim 1, but does not teach the semiconductor device wherein the dopant implant region comprises an argon dopant.
Wann teaches a semiconductor device (201, FIG. 2A, [0021]) wherein the dopant implant region comprises an argon dopant (argon is implanted into the dielectric layer 231, 233, 235, 237, and 239 as an etch accelerator, and the resulting dopant concentration profile leaves a concentration tail within the dielectric layer, [0021, 0029, 0038-0042]).
As taught by Wann, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren in view of Chen to obtain and achieve the semiconductor device wherein the dopant implant region comprises an argon dopant as claimed, because argon ion implantation structurally weakens the dielectric material, thereby increasing its etch rate during a subsequent etching process, [0029].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wann in combination with Apelgren in view of Chen due to the above reason.
Regarding claim 7, Apelgren in view of Chen teaches the semiconductor device of claim 1, but does not teach the semiconductor device wherein the doped implant region has a concentration of dopants of between about 1E15 and about 5E15.
Wann teaches the semiconductor device (201, FIG. 2A, [0021]) the doped implant region has a concentration of dopants of between about 1E15 and about 5E15 (the dielectric layer is implanted at dopant concentrations ranging from about 5E14 to about 5E15 atoms/cm2, [0027, 0043]).
Note: Because claim 7 does not specify a unit for the recited dopant concentration, the phrase “a concentration of dopants of between about 1E15 and about 5E15” is interpreted as encompassing an implantation dose expressed in atoms/cm2.
As taught by Wann, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren in view of Chen to obtain and achieve the semiconductor device wherein the doped implant region has a concentration of dopants of between about 1E15 and about 5E15 as claimed, because selecting implantation concentration within this range permits predictable control of the etch rate of the dielectric material [0027-0028]. Further, it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wann in combination with Apelgren in view of Chen due to the above reason.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Apelgren (US 20030013296) in view of Chen (US 2016/0027729), and further in view of Gambino et al. (US 2004/0171201; hereinafter ‘Gambino’).
Regarding claim 4, Apelgren in view of Chen teaches the semiconductor device of claim 1, but does not teach the semiconductor device wherein the dopant implant region comprises a dopant selected from the group consisting of fluorine (F), difluoroboron (BF2), and combinations thereof.
Gambino teaches a semiconductor device (FIG. 5, [0015, 0018]) wherein the dopant implant region comprises a dopant selected from the group consisting of F, BF2, and combinations thereof (fluorine is implanted at an angle into dielectric oxide sidewall spacers to form fluorine-doped low-k dielectric sidewall regions, [0021-0022, 0034]).
As taught by Gambino, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren in view of Chen to obtain and achieve the semiconductor device wherein the dopant implant region comprises a dopant selected from the group consisting of F, BF2, and combinations thereof as claimed, because fluorine implantation reduces the dielectric constant and corresponding capacitance of dielectric material adjacent a conductive structure [0007-0008].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Gambino in combination with Apelgren in view of Chen due to the above reason.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Apelgren (US 20030013296) in view of Chen (US 2016/0027729), and Gambino (US 2004/0171201), and further in view of Rainville et al. (US 2018/0197770; hereinafter ‘Rainville’).
Regarding claim 5, Apelgren in view of Chen, and Gambino teaches the semiconductor device of claim 14, but does not teach the semiconductor device wherein the etch stop layer comprises aluminum oxide.
Rainville teaches a semiconductor device [0006] wherein the etch stop layer comprises aluminum oxide (109 comprises aluminum oxide, FIG. 1C, [0043]).
As taught by Rainville, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren in view of Chen, and Gambino to obtain and achieve the semiconductor device wherein the etch stop layer comprises aluminum oxide as claimed, because aluminum oxide provides good etch selectivity relative to the overlying interlayer dielectric material and protects the underlying metallization layer during formation of an interconnect opening [0044, 0053].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Rainville in combination with Apelgren in view of Chen, and Gambino due to the above reason.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Apelgren (US 2003/0013296) in view of Chen (US 2016/0027729), and further in view of Al-Bayati et al. (US 2005/0191828; hereinafter ‘Al-Bayati’).
Regarding claim 6, Apelgren in view of Chen teaches the semiconductor device of claim 1, but does not teach the semiconductor device wherein a dopant concentration in the doped implant region is in a range of 50% concentration by volume.
Al-Bayati teaches a semiconductor device [0007] wherein a dopant concentration in the doped implant region is in a range of 50% concentration by volume (argon is ion implanted into insulating layer 320 and forms gas bubbles 330 therein, wherein the total volume occupied by 330 within 320 increases from zero toward 50%, FIG. 3, [0046]).
As taught by Al-Bayati, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren in view of Chen to obtain and achieve the semiconductor device wherein a dopant concentration in the doped implant region is in a range of 50% concentration by volume as claimed, because the implanted gaseous species reduces the dielectric constant of the dielectric layer, thereby reducing capacitive coupling between conductive features [0046]. Further, it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Al-Bayati in combination with Apelgren in view of Chen due to the above reason.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Apelgren (US 20030013296) in view of Ting et al. (US 2016/0093566; hereinafter ‘Ting’).
Regarding claim 13, Apelgren teaches the semiconductor device of claim 9, but does not teach the semiconductor device wherein the metal plug has a first width at the top of the interlayer dielectric layer, has a second width less than the first width at the bottom of the interlayer dielectric layer, and has a third equal to the second width at the bottom of the etch stop layer.
Ting teaches a semiconductor device (100, FIG. 11, [0027, 0055]) wherein
the metal plug (204, [0030]) has a first width at the top of the interlayer dielectric layer (a first width W11 at the top of 202, [0030], see the annotated in FIG. 11),
has a second width less than the first width at the bottom of the interlayer dielectric layer (a second width W22 less than W11 at the bottom of 202, see the annotated in FIG. 11), and
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has a third equal to the second width at the bottom of the etch stop layer (W33 equal to W22 at the bottom of 150, since the lower via portion 203 formed by filling the same substantially vertical via trench 702 extending through the bottom of 202 and 150, FIGS. 3 and 7, [0039, 0047], see the annotated in FIG. 11).
As taught by Ting, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren to obtain and achieve the semiconductor device wherein the metal plug has a first width at the top of the interlayer dielectric layer, has a second width less than the first width at the bottom of the interlayer dielectric layer, and has a third equal to the second width at the bottom of the etch stop layer as claimed, because the metal plug configuration provides a continuous conductive path and reliable electrical connection to the underlying metal line [0002, 0030-0031].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ting in combination with Apelgren due to the above reason
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Apelgren (US 20030013296) in view of Wann (US 2013/0221491).
Regarding claim 16, Apelgren teaches the semiconductor device of claim 9, but does not teach the semiconductor device wherein the doped region comprises an argon dopant.
Wann teaches a semiconductor device (201, FIG. 2A, [0021]) wherein the doped region comprises an argon dopant (argon is implanted into the dielectric layer 231, 233, 235, 237, and 239 as an etch accelerator, and the resulting dopant concentration profile leaves a concentration tail within the dielectric layer, [0021, 0029, 0038-0042]).
As taught by Wann, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren to obtain and achieve the semiconductor device wherein the dopant implant region comprises an argon dopant as claimed, because argon ion implantation structurally weakens the dielectric material, thereby increasing its etch rate during a subsequent etching process, [0029].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wann in combination with Apelgren due to the above reason.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Apelgren (US 20030013296) in view of Gambino (US 2004/0171201).
Regarding claim 17, Apelgren teaches the semiconductor device of claim 9, but does not teach the semiconductor device wherein the doped region comprises a dopant selected from the group consisting of fluorine (F), difluoroboron (BF2), and combinations thereof.
Gambino teaches a semiconductor device (FIG. 5, [0015, 0018]) wherein the doped region comprises a dopant selected from the group consisting of F, BF2, and combinations thereof (fluorine is implanted at an angle into dielectric oxide sidewall spacers to form fluorine-doped low-k dielectric sidewall regions, [0021-0022, 0034]).
As taught by Gambino, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren to obtain and achieve the semiconductor device wherein the doped region comprises a dopant selected from the group consisting of F, BF2, and combinations thereof as claimed, because fluorine implantation reduces the dielectric constant and corresponding capacitance of dielectric material adjacent a conductive structure [0007-0008].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Gambino in combination with Apelgren due to the above reason.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Apelgren (US 20030013296) in view of Gambino (US 2004/0171201), and further in view of Rainville (US 2018/0197770).
Regarding claim 18, Apelgren in view of Gambino teaches the semiconductor device of claim 17, but does not teach the semiconductor device wherein the etch stop layer comprises aluminum oxide.
Rainville teaches a semiconductor device [0006] wherein the etch stop layer comprises aluminum oxide (109 comprises aluminum oxide, FIG. 1C, [0043]).
As taught by Rainville, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren in view of Gambino to obtain and achieve the semiconductor device wherein the etch stop layer comprises aluminum oxide as claimed, because aluminum oxide provides good etch selectivity relative to the overlying interlayer dielectric material and protects the underlying metallization layer during formation of an interconnect opening [0044, 0053].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Rainville in combination with Apelgren in view of Gambino due to the above reason.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Apelgren (US 20030013296) in view of Hiroi et al. (US 2013/0285203; hereinafter ‘Hiroi’).
Regarding claim 19, Apelgren teaches a semiconductor device (FIG. 19, [0018, 0022]), comprising:
a metallization layer (1125, [0024, 0039]) over a semiconductor substrate (1100, [0039]);
an etch stop layer (1110, [0040]) over the metallization layer (1125), the etch stop layer comprising a material selected from the group consisting a metal oxide, a nitride, a carbide, a boride, and combinations thereof (1110 comprises a nitride, [0040]);
an interlayer dielectric layer (1120, [0040]) over the etch stop layer (1110);
a metal plug (a metal plug including 1640, 1725A, and 1725B, FIGS. 17 and 19, [0050]; hereinafter ‘MP’)
extending through the interlayer dielectric layer and through the etch stop layer (MP extending through 1120 and through 1110, FIG. 19), and
electrically contacting the metallization layer (MP is electrically connected to 1125, FIG. 15, [0047, 0050-0051]), and
a doped region (a dopant implant region including 1420 and 1430, FIG. 14, [0043]; hereinafter ‘DR’) of the interlayer dielectric layer (1120) surrounding the metal plug (1420 of DR surrounding 1640, FIG. 19); and
an undoped region (an undoped region excepting 1420 and 1430 of 1120 and 1130, FIG. 14, [0043]; hereinafter ‘UDR’) of the interlayer dielectric layer (1120) surrounding the doped region of the interlayer dielectric layer (UDR of 1120 surrounding 1420, FIG. 19).
Apelgren does not teach the semiconductor device comprising a porous interlayer dielectric layer comprising a material selected from the group consisting of SiOCN, SiCN and SiOC.
Hiroi teaches a semiconductor device (FIG. 4, [0002, 0095]) comprising a porous interlayer dielectric layer (29b, [0100]) comprising a material selected from the group consisting of SiOCN, SiCN and SiOC (29b comprises porous SiOC, [0100]).
As taught by Hiroi, one of ordinary skill in the art would utilize and modify the above teaching into Apelgren to obtain and achieve the semiconductor device comprising a porous interlayer dielectric layer comprising a material selected from the group consisting of SiOCN, SiCN and SiOC as claimed, because a low-dielectric-constant interlayer dielectric layer reduces interconnection capacitance and thereby reduces capacitive coupling between adjacent conductive features [0068, 0077].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hiroi in combination with Apelgren due to the above reason.
Regarding claim 20, Apelgren in view of Hiroi teaches the semiconductor device of claim 19, wherein the doped region extends along a topmost surface of interlayer dielectric layer (Apelgren: 1430 of DR extends along a topmost surface of 1120, FIG. 19) and extends from the topmost surface of the interlayer dielectric layer to topmost surface of the etch stop layer (1420 of DR extends from the topmost surface of 1120 to topmost surface of 1110, FIG. 19).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that Li et al. (US 2015/0091181), Ting et al. (US 2014/0264873), TSAI et al. (US 2017/0345706) as a semiconductor device with a metal plug, an interlayer dielectric layer, and a etch stop layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/4/26
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