DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
HEAT DISSIPATING IN A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Fritz et al. [US Patent 6949404] in view of Iruvanti et al. [US PGPUB 20120018873] and Hyung [US PGPUB 20190043777] (hereinafter Fritz and Iruvanti).
Regarding claim 1, referring to Fig. 1 of Fritz, Fritz teaches a semiconductor device, comprising:
a circuit substrate (104, Col. 2, line 36);
a semiconductor chip (102 Col. 2, line 35), and
a cover (110/112, Fig. 1), comprising:
a cap block (thermal compound 110 and portion of 112 in contacting it), overlying the semiconductor package (Fig. 1); and
a support (portion of 112 in contact with adhesive 114), disposed between the cap block and the circuit substrate (Fig. 1), and extending towards the circuit substrate (Fig. 1),
wherein a region of a bottom surface of the cap block has a curved profile matching a warpage profile of the semiconductor chip (Fig. 1), and the region having the curved profile extends over the semiconductor chip (Fig. 1), and the support is laterally spaced from the cap by a gap.
Fritz fails to specifically disclose a semiconductor chip is a semiconductor package and wherein the cover is metallic cover.
Referring to the invention of Iruvanti teaches a cover 130/140 to be a metallic cover (Fig. 1).
In view of such teaching by Iruvanti, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the cover of Fritz invention be metallic in order to have optimal heat dissipation in the packaged device.
Referring to the invention of Hyung, Hyung teaches the structures of various semiconductor devices, wherein instead of having a semiconductor device including a single semiconductor chip, a semiconductor device with multiple chips (semiconductor package) can be implemented (Figs. 2, 7, 9, 11, 15 and 16).
In view of such teaching by Hyung, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Fritz include a semiconductor package instead of a semiconductor chip in order to increase the device’s functional capacity.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hyung in view of Fritz.
Regarding claim 10, Hyung teaches a semiconductor device, comprising:
a substrate (102-2, Para 81);
a first semiconductor package (left 110a and 130a, Fig. 14) and a second semiconductor package (right 110a and 130a, Fig. 14, Para 82), disposed over the substrate and laterally next to one another (Fig. 14);
a thermal interface material (170, Para 82), disposed over a first rear surface of the first semiconductor package further away from the substrate and a second rear surface of the second semiconductor package further away from the substrate (Fig. 14);
a cap (150-4, Para 82), extending on the thermal interface material over the first semiconductor package and the second semiconductor package (Fig. 14);
wherein the first rear surface of the first semiconductor package and the second rear surface of the second semiconductor package each present a warped profile (Fig. 14),
wherein the cap includes a first region in direct contact with the thermal interface material over the first semiconductor package and a second region in direct contact with the thermal interface material over the second semiconductor package (Fig. 14), and
wherein a thickness of the cap varies throughout the first region and the second region (Fig. 14), the thickness being measured along a vertical stacking direction of the circuit substrate, the first semiconductor package, and the thermal interface material (Fig. 14).
Hyung does not specifically disclose that the substrate is circuit substrate, the cap is a metallic cap,
a first underfill, disposed between the first semiconductor package and the circuit substrate; and
a second underfill, disposed between the second semiconductor package and the circuit substrate, the first underfill being laterally separated from the second underfill by a gap.
However, in the embodiment of Fig. 2, Hyung discloses that substrate 102 (similar to substrate 102-2) is a printed circuit board (Para 28) and that cap 150 (similar to cap 150-4) is a metallic cap (Para 38).
In view of such further teaching by Hyung, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the substrate and cap of Hyung’s Fig. 14 be a circuit substrate and a metallic cap at least based on the rationale of relying on teachings, suggestions, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G) -wherein such modification would result the ability to drive the device and provide adequate heat dissipation in the device.
Referring to the invention of Fritz, Fritz discloses a method of bonding semiconductor chip 102 to circuit substrate 104, and wherein an underfill 108 is disposed between the first semiconductor chip and the circuit substrate (Fig. 1, Col. 2, lines 35-38).
In view of such teaching by Fritz, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Hyung comprise the teachings of Fritz at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C) –wherein such an implementation would improve the structural integrity of the device.
Thus, a person having ordinary skills in the art will understand that the limitation regarding the underfill material not specifically disclosed by Hyung would be obviously met. That is, a first underfill and a second underfill will be disposed between the first semiconductor package and the circuit substrate; and between the second semiconductor package and the circuit substrate, and that the first underfill will be laterally separated from the second underfill by a gap (gap based on molding layer 190).
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 2-9 and 11-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claims 18-20 are allowed because all prior arts of record and related prior arts not of record either singularly or in combination fail to anticipate or render obvious a semiconductor device, comprising:
a cover comprising a plurality of outer flanges, disposed at edges of the cap (as claimed in claim 18), in combination with the rest of claim limitations as claimed and defined by the Applicant.
Claims 2-5 and 7-8 are objected to because the prior arts of record and related prior arts fail to anticipate or render obvious the limitations of claims 2-5 and 7-8 respectively. Although individual elements of claims may be found in one of more of the prior arts, none of the prior arts, alone or in combination, teaches or suggests the particularly claimed combination of individual elements or the relationship of the claimed individual elements. Wherein any combination of the prior arts to arrive at the claimed combination would be nothing short of impermissible hindsight.
Claims 6 and 9 are allowable based on their dependency on claims 5 and 8 respectively.
Claims 11, 13, 15 and 16 are objected to because the prior arts of record and related prior arts fail to anticipate or render obvious the limitations of claims 11, 13, 15 and 16 respectively. Although individual elements of claims may be found in one of more of the prior arts, none of the prior arts, alone or in combination, teaches or suggests the particularly claimed combination of individual elements or the relationship of the claimed individual elements. Wherein any combination of the prior arts to arrive at the claimed combination would be nothing short of impermissible hindsight.
Claims 12, 14 and 17 are allowable based on their dependency on claims 11, 13, 15 and 16 respectively.
Prior Arts
Listed in the attached PTO-892 Form are a prior arts determined to be the closest prior art to the claimed invention. The prior art however fails to disclose the allowable subject of the current invention. For example,
Regarding claim 18, referencing Fig. 14 of Hyung [US PGPUB 20190043777], Hyung teaches
18. A semiconductor device, comprising:
a substrate (102; wherein the substrate can obviously be a circuit substrate, Hyung, Para 28) having a warpage profile with at least concave regions and one convex region;
a semiconductor package (110a/130a), disposed on the circuit substrate; and
a cover (150-4, wherein the cover can obviously be a metallic cover, Hung, Para 38), comprising:
a cap (150-4); and
wherein a region of a bottom surface of the cap has a curved profile matching the warpage profile of the circuit substrate, and the region having the curved profile extends over the semiconductor package, and
a material of the metallic cover comprises silver diamond (where Bonnet et al. [US PGPUB 20160135280] makes it obvious to use silver diamond as a substitute to silver).
However, Hyung and Bonnet fail to disclose that the cover comprises a plurality of outer flanges, disposed at edges of the cap. Wherein any combination of the prior arts to arrive at the claimed combination would be nothing short of impermissible hindsight.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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