DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fillion et al. (US 5353498).
Regarding claim 1, Fillion teaches a semiconductor structure (Figs. 1a-1e of Fillion), comprising:
a die (14) including a top surface (top surface of 14);
a molding (24) the die, wherein the molding includes a top surface (top surface of 24); and
a polymer (12a-12b, as described in column 5 line 36-40) over the die and the molding, wherein the polymer has a first bottom surface (interface of 12a and die 14) contacting the die and a second bottom surface (interface of 12a and molding 24) contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface (as shown in Fig. 1e).
Regarding claim 2, Fillion teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the polymer is conformal to the top surface of the molding and the top surface of the die (as shown in Fig. 1e of Fillion).
Regarding claim 4, Fillion teaches all limitations of the semiconductor structure of claim 1, and further comprising a redistribution layer (interconnect 28 in Fig. 1e of Fillion) over the polymer.
Claims 8-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2013/0001776 A1).
Regarding claim 8, Yu teaches a semiconductor structure (200 in Fig. 12 of Yu), comprising:
a die (chip 20, which is labeled in Fig. 7) including a top surface (top surface 32 of chip 20);
a molding (46) surrounding the die, wherein the molding includes a top surface (top surface 46A); and
a polymer (66-49-54, as described in [0019]-[0020]) over the top surface of the die and over the top surface of the molding, wherein the polymer has a first bottom surface (interface of 66 and chip 20) contacting the die and a second bottom surface (interface of 49 and molding 46) contacting the molding, and the first bottom surface and the second bottom surface are at different levels (as shown in Fig. 12 of Yu).
Regarding claim 9, Yu teaches all limitations of the semiconductor structure of claim 8, and also teaches wherein the molding is in contact with a sidewall of the die entirely (as shown in Fig. 12 of Yu).
Regarding claim 10, Yu teaches all limitations of the semiconductor structure of claim 8, and also teaches wherein the polymer is conformal to the top surface of the molding and the top surface of the die (as shown in Fig. 12 of Yu).
Regarding claim 11, Yu teaches all limitations of the semiconductor structure of claim 8, and further comprising a redistribution layer (PPI 50 in Fig. 12 of Yu) over the polymer.
Regarding claim 12, Yu teaches all limitations of the semiconductor structure of claim 11, and also teaches wherein the redistribution layer comprises a bond pad (portion of 50 that is in contact with bump 60) electrically connected to the die.
Regarding claim 13, Yu teaches all limitations of the semiconductor structure of claim 12, and also teaches wherein the redistribution layer comprises a conductive trace (portion of PPI 50 that is connected to contacts 34 to the bond pad) between the die and the bond pad, and the bond pad is electrically connected to the die by the conductive trace (as shown in Fig. 12 of Yu).
Regarding claim 14, Yu teaches all limitations of the semiconductor structure of claim 12, and further comprising a conductive bump (60) over the bond pad.
Regarding claim 15, Yu teaches all limitations of the semiconductor structure of claim 14, and also teaches wherein the die is electrically connected to a substrate (the presence of an external substrate is implied by the bumps 60) through the conductive bump.
Claims 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (US 2014/0048959 A1).
Regarding claim 16, Hu teaches a semiconductor structure (180 in Fig. 14 of Hu), comprising:
a first die (1021) including a first top surface (top surface of 1021);
a second die (1022) including a second top surface (top surface of 1022);
a molding (122) surrounding the first die and the second die, wherein the molding includes a third top surface; and
a polymer (1621) over the first die, the second die, and the molding, wherein the polymer has a first bottom surface (interface of 1621 and 1021) over the first die, a second bottom surface (interface of 1621 and 1022) over the second die and a third bottom surface (interface of 1621 and 122) over the molding, and the second bottom surface is at a level substantially same as the third bottom surface (as shown in Fig. 14 of Hu).
Regarding claim 17, Hu teaches all limitations of the semiconductor structure of claim 16, and also teaches wherein the first bottom surface is at a level substantially lower than the second bottom surface (as shown in Fig. 14 of Hu).
Regarding claim 18, Hu teaches all limitations of the semiconductor structure of claim 16, and also teaches wherein the third top surface of the molding is at a level substantially higher than the first bottom surface of the polymer (as shown in Fig. 14 of Hu).
Regarding claim 19, Hu teaches all limitations of the semiconductor structure of claim 16, and further comprising a substrate (the presence of external substrate to which the package 180 is mounted on is implied by the solder balls 176), wherein the first die, the second die, the molding and the polymer are disposed over the substrate.
Regarding claim 20, Hu teaches all limitations of the semiconductor structure of claim 16, and further comprising a redistribution layer (170 in Fig. 14 of Hu) over the polymer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Fillion, as applied above, and further in view of Yu et al. (US 2013/0001776 A1).
Regarding claim 3, Fillion teaches all limitations of the semiconductor structure of claim 1, but does not teach the semiconductor structure further comprising a substrate, wherein the die, the molding and the polymer are disposed over the substrate.
Yu teaches a semiconductor structure (200 in Fig. 6 of Yu) comprising: a substrate (42), wherein a die (42), a molding (46) and a polymer (49-54) are disposed over the substrate; a redistribution layer (50) including a conductive trace (portion of 50 in contact with contacts 34) and a bond pad (portion of 50 in contact with bump 60); a plurality of bumps (60).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the solder bumps to the interconnect of Fillion in order to make better electrical contact to external circuit.
Regarding claim 5, Fillion in view of Yu teaches all limitations of the semiconductor structure of claim 4, and also teaches wherein the redistribution layer comprises a bond pad electrically connected to the die (as taught in claim 4 above).
Regarding claim 6, Fillion in view of Yu teaches all limitations of the semiconductor structure of claim 5, and also teaches wherein the redistribution layer comprises a conductive trace (electrical interconnect from contact 34 to the pad underneath the bump 60) between the die and the bond pad, and the bond pad is electrically connected to the die by the conductive trace.
Regarding claim 7, Fillion in view of Yu teaches all limitations of the semiconductor structure of claim 5, and further comprising a conductive bump (60 in Fig. 6 of Yu) over the bond pad.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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