DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to an Application filed on 07/18/2024.
Currently, claims 1-20 are examined as below.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Method of Manufacturing an Optical Sensor Comprising a Self-aligned Silicide Layer and a Non-self-aligned silicide layer
(Clean Version) Method of Manufacturing an Optical Sensor Comprising a Self-aligned Silicide Layer and a Non-self-aligned silicide layer
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 6 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2009/0243019 A1 to Kawai.
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Regarding independent claim 1, Kawai in Figs. 1A-1B and 6-10A teaches a method of manufacturing a semiconductor structure 1 (¶ 25, optical sensor or semiconductor chip 1), the method comprising:
forming a light-absorption layer 3, 5 (Figs. 1A-1B, 6, 9, 10A, ¶ 25, ¶ 27 & ¶ 96-¶ 97, visible light sensor 3 absorbs visible light and/or ultraviolet ray sensor 5 absorb ultraviolet light) in a substrate 10 (¶ 25, SOI substrate 10), wherein the light-absorption layer 3, 5 includes an upper surface above an upper surface of the substrate 10 (Figs. 1A-1B, 9, ¶ 27, ¶ 35);
forming a first doped region 47 (¶ 36, n-type first high-concentration region 47) and a second doped region 48 (¶ 36, p-type second high-concentration region 48) in the light-absorption layer 3, 5 adjacent to the first doped region 47 (Fig. 6);
depositing a first patterned mask layer 37-38, 57-58 (Figs. 7A-8B, ¶ 88, insulating films 37-38 and 57-58 formed by etching the insulating films 95-96) over the light-absorption layer 3, 5 (Fig. 8A), wherein the first patterned mask layer 37-38, 57-58 includes an opening (Figs. 8A-8B, opening that exposes region 48) exposing the second doped region 48 and overs at least partially the first doped region 47 (Figs. 8A-8B);
forming a first silicide layer 52 (¶ 89, silicide region 52) in the opening on the second doped region 48 (Fig. 8B); and
forming a second silicide layer 52 (¶ 89, silicon region 52) on the first doped region 47 (Fig. 8B).
Regarding claim 3, Kawai in Figs. 8A-8B further teaches forming a first silicide layer 52 (¶ 89, silicide region 52) comprising depositing a metallic material (¶ 89, a film of metal) over the first patterned mask layer 37-38, 57-58 and within the opening (Figs. 8A-8B & ¶ 89), wherein the first silicide layer 52 is formed in a bottom of the opening (Fig. 8B).
Regarding claim 6, Kawai in Figs. 1A-1B, 6 and 9 further teaches depositing a semiconductor layer 13 (¶ 26, SOI layer 13 is a semiconductor layer) over the light-absorption layer 3, 5 (Figs. 1A-1B, 6 & 9, the layer 13 is over an upper surface of sensor 3 and over side surfaces of sensor 5), wherein the first doped region 47 and the second doped region 48 are also formed in the semiconductor layer 13 (Figs. 1B, 6 & 9).
Regarding claim 11, Kawai in Fig. 1A further teaches the first doped region 47 laterally at least partially surrounds the second doped region 48 from a top-view perspective (Fig. 1A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kawai in view of US 2014/0339614 A1 to Fang et al. (“Fang”).
Regarding claim 2, Kawai in Fig. 1B teaches the light-absorption layer 3, 5 is formed in a substrate 10 (¶ 24 & ¶ 26, substrate 10), which is an SOI substrate 10 includes a semiconductor support substrate 11 formed of silicon, a buried oxide film 12 and a SOI layer 13 formed of silicon (¶ 26). That is, the light-absorption layer 3, 5 comprises silicon of the substrate 10 (Fig. 1B).
Kawai does not explicitly disclose the light-absorption layer comprises germanium.
Fang, however, teaches that a substrate can be made from silicon-on-insulator or germanium-on-insulator (¶ 105, ¶ 120 & ¶ 152). In other words, Fang recognizes that silicon-on-insulator and germanium-on-insulator are functional equivalent as being able to function as substrates.
According to Section 2144.06.II, "In order to rely on equivalence as a rationale supporting an obviousness rejection, the equivalency must be recognized in the prior art" In re Ruff, 256 F.2d 590, 118 USPQ 340 (CCPA 1958). The Section 2144.06.II further states that "An express suggestion to substitute one equivalent component or process for another is not necessary to render such substitution obvious. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable and obvious over Kawai.
Regarding claim 10, Kawai in Figs. 1B and 8B-9 does not explicitly disclose the first silicide layer 52 (of region 48) comprises a width greater than a width of the second silicide layer 52 (of region 47).
However, it would have been obvious to form the widths within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).”
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 4-5, 7-9 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim.
Claim 4 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 4, forming a trench in the substrate, wherein forming a light-absorption layer comprises forming a second patterned mask layer over the substrate and the trench is formed according to the second patterned mask layer.
Claim 5 would be allowable, because claim 5 depends from the allowable claim 4.
Claim 7 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 7, depositing a dielectric layer over the first patterned mask layer and exposing the first doped region and the first silicide layer.
Claims 8-9 would be allowable, because they depend from the allowable claim 7.
Claim 12 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 12, wherein the first doped region and the second doped region are configured to form a switch, wherein the second doped region is configured to receive electrons converted from photons received by the light-absorption layer.
Claims 13-20 are allowed
Regarding independent claim 13, Kawai in Figs. 1A-1B and 6-10A teaches a method of manufacturing a semiconductor structure 1 (¶ 25, optical sensor or semiconductor chip 1), the method comprising:
forming a light-absorption layer 3, 5 (Figs. 1A-1B, 6, 9, 10A, ¶ 25, ¶ 27 & ¶ 96-¶ 97, visible light sensor 3 and ultraviolet ray sensor 5 absorb respective ultraviolet light and visible light) in a substrate 10 (¶ 25, SOI substrate 10), wherein the light-absorption layer 3, 5 includes an upper surface above an upper surface of the substrate 10 (Figs. 1A-1B, 9, ¶ 27, ¶ 35);
forming a first doped region of a first conductivity type 47 (¶ 36, n-type first high-concentration region 47) and a second doped region of a second conductivity type 48 (¶ 36, p-type second high-concentration region 48) in the light-absorption layer 3, 5 adjacent to the first doped region 47 (Fig. 6);
forming a self-aligned silicide layer 52 (¶ 89-¶ 90, silicide region 52) arranged over and aligned with the second doped region 48 (Fig. 8B).
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 13, forming a non-self-aligned silicide layer over and aligned with the first doped region.
Therefore, independent claim 13 is allowed.
Claims 14-16 are allowed, because they depend from the allowed claim 13.
Regarding independent claim 17, Kawai in Figs. 1A-1B and 6-10A teaches a method for manufacturing a semiconductor structure 1 (¶ 25, optical sensor or semiconductor chip 1), comprising:
forming a light-absorption layer 3, 5 (Figs. 1A-1B, 6, 9, 10A, ¶ 25, ¶ 27 & ¶ 96-¶ 97, visible light sensor 3 and ultraviolet ray sensor 5 absorb respective ultraviolet light and visible light) in a substrate 10 (¶ 25, SOI substrate 10), wherein the light-absorption layer 3, 5 includes an upper surface above an upper surface of the substrate 10 (Figs. 1A-1B, 9, ¶ 27, ¶ 35);
forming a first doped region of a first conductivity type 47 (¶ 36, n-type first high-concentration region 47) and a second doped region of a second conductivity type 48 (¶ 36, p-type second high-concentration region 48) in the light-absorption layer 3, 5 adjacent to the first doped region 47 (Fig. 6);
forming a patterned mask layer 37-38, 57-58 (Figs. 7A-8B, ¶ 88, insulating films 37-38 and 57-58 formed by etching the insulating films 95-96) comprising a first opening (Figs. 8A-8B, opening that exposes region 48) and a first conductive material (Fig. 8B, ¶ 89, a film of metal for forming a silicide) in the first opening;
forming a patterning dielectric layer 14 (Fig. 9, ¶ 56, ¶ 93, intermediate insulating film 14, formed of silicon dioxide, including contact holes 40, 51, 71, 74) arranged over the patterned mask layer 37-38, 57-58 and comprising a second opening (Fig. 9, ¶ 93, contact hole 40, 51, 71, 74) and a second conductive material (¶ 91, ¶ 93, contact plug 36, 50, 70, 73; ¶ 57-¶ 59, contact plug 36, 50, 70, 73 is formed of a conductive material) in the second opening 40, 51, 71, 74 (Fig. 9).
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 17, converting the first conductive material and the second conductive material into a first silicide layer and a second silicide layer, respectively.
Therefore, independent claim 17 is allowed.
Claims 18-20 are allowed, because they depend from the allowed claim 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2018/0190702 A1 to Na et al. relates to an optical apparatus including a semiconductor substrate; a first light absorption region supported by the semiconductor substrate; one or more first switches controlled by a first control signal; one or more second switches controlled by a second control signal; and a counter-doped region formed in a first portion of the first light absorption region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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