DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 & 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US Pub no. 2011/0212579 A1)
Regarding claim 1, Chen et al discloses An integrated chip (IC), comprising: a semiconductor substrate(200)[0025]; a semiconductor layer(222) disposed over the semiconductor substrate(200)[0032]; and an insulating structure (210)buried between the semiconductor substrate(200) and the semiconductor layer(222)[0032], wherein: the insulating structure(210) has a first region(202) and a second region(204)[0028]; the insulating structure (210)has a first thickness (tcore)in the first region (202)of the insulating structure(210); and the insulating structure(210) has a second thickness (t I/O)different than the first thickness in the second region (204)of the insulating structure(210) fig. 2c/ fig. 2e[0030].
Regarding claim 2, Chen et al discloses wherein the semiconductor layer (222)has a substantially planar upper surface fig. 2e.
Regarding claim 5, Chen et al discloses further comprising: a pair of first source/drain regions (see fig. 2e)disposed in the semiconductor layer(222) and directly over the first region(202) of the insulating structure(210) [0038]; and a pair of second source/drain regions (see fig. 2e)disposed in the semiconductor layer (222)and spaced from the first source/drain regions fig. 2e, wherein the second source/drain regions are disposed directly over the second region (204)of the insulating structure(210) fig. 2e.
Regarding claim 6, Chen et al discloses further comprising: a first gate dielectric disposed over the semiconductor layer and between the first source/drain regions (gate dielectric and source/drain features shown in fig. 2e)[0038], wherein the first gate dielectric is spaced from the semiconductor substrate by a first distance(gate dielectric and source/drain features shown in fig. 2e)[0038]; and a second gate dielectric disposed over the semiconductor layer (222)and between the second source/drain regions(gate dielectric and source/drain features shown in fig. 2e)[0038], wherein the second gate dielectric is spaced from the semiconductor substrate by a second distance that is substantially the same as the first distance(gate dielectric and source/drain features shown in fig. 2e).
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Holt (US Pub no. 2006/0214225 A1).
Regarding claim 1, Holt et al discloses An integrated chip (IC) fig. 3a, comprising: a semiconductor substrate(22)[0042]; a semiconductor layer (12)disposed over the semiconductor substrate(22)[0042]; and an insulating structure (16)buried between the semiconductor substrate(22) and the semiconductor layer(12) fig. 3a), wherein: the insulating structure(16) has a first region (42)and a second region(44)[0049]; the insulating structure (16)has a first thickness in the first region(42) of the insulating structure(16); and the insulating structure(16) has a second thickness different than the first thickness in the second region of the insulating structure(16) fig. 3a[0020].
Regarding claim 2, Holt et al discloses wherein the semiconductor layer (12)has a substantially planar upper surface fig. 3a.
Regarding claim 3, Holt et al discloses wherein the semiconductor substrate(22) has a substantially planar upper surface fig. 3a.
Regarding claim 4, Holt et al discloses wherein: the insulating structure(16) comprises one or more dielectric layers[0024] and one or more filler structures(40); and the one or more dielectric layers [0024]separate the one or more filler structures(40) from both the semiconductor substrate(22) and the semiconductor layer(16).
Regarding claim 5, Holt et al discloses further comprising:
a pair of first source/drain regions (42-source/drain)disposed in the semiconductor layer [0050]and directly over the first region(42) of the insulating structure(16); and a pair of second source/drain regions(44-source drain) disposed in the semiconductor layer (12)and spaced from the first source/drain regions(42-source/drain), wherein the second source/drain regions(44-source/drain) are disposed directly over the second region of the insulating structure(16) [0050] fig. 3a.
Regarding claim 6, Holt et al discloses further comprising: a first gate dielectric disposed over the semiconductor layer (12) and between the first source/drain regions[0050], wherein the first gate dielectric is spaced from the semiconductor substrate (22)by a first distance[0050]; and a second gate dielectric disposed over the semiconductor layer (12)and between the second source/drain regions [0050] wherein the second gate dielectric is spaced from the semiconductor substrate (22)by a second distance that is substantially the same as the first distance[0050] fig. fig. 3a/3b.
Claim(s) 10-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by An (US Patent 6,414,355 B1)
Regarding claim 10, An et al discloses an integrated chip (IC), comprising: a semiconductor substrate(16) (col. 4, lines 14-15); an insulating structure(30/14) disposed over the semiconductor substrate(16); and a semiconductor layer (12”)disposed over the insulating structure(30/14)(col. 4. Lines 64-65), wherein:
an upper surface of the semiconductor layer(12”) is substantially planar fig. 7e; the upper surface of the semiconductor layer(12”) overlies both a first lower surface of the semiconductor layer(thicker areas of 12”) and a second lower surface of the semiconductor layer(thinner areas of 12”) (col. 5 lines 5-12); the first lower surface of the semiconductor layer(thicker areas of 12”) is vertically spaced from the upper surface of the semiconductor layer(12”) by a first distance fig. 7e; and the second lower surface of the semiconductor layer (thinner areas of 12”) is vertically spaced from the upper surface of the semiconductor layer by a second distance different than the first distance fig. 7e(col. 5 lines 5-12).
Regarding claim 11, An et al discloses wherein a sidewall of the semiconductor layer (12”)extends continuously from the first lower surface of the semiconductor layer to the second lower surface of the semiconductor layer(12”) fig. 7e.
Regarding claim 12, An et al discloses wherein the sidewall of the semiconductor layer (12”)is substantially vertical(fig. 7e).
Regarding claim 13, An et al discloses further comprising: a first isolation structure (18 of region 22d)disposed in the semiconductor layer (12”)and over the first lower surface of the semiconductor layer(thicker areas of 12”)(Col 2, lines 64-65) fig. 7e, wherein a bottom surface of the first isolation structure(18 of region 22d) is vertically spaced a third distance from the semiconductor substrate(12”) fig. 7e/1a; and a second isolation structure (18 of region 22a))disposed in the semiconductor layer (12”)and over the second lower surface of the semiconductor layer(thinner areas of 12”), wherein a bottom surface of the second isolation structure is vertically spaced from the semiconductor substrate a fourth distance different than the third distance fig. 7e.
Regarding claim 14, An et al discloses further comprising: a pair of first source/drain regions (claim 8)disposed in the semiconductor layer(12”) and directly over the first lower surface of the semiconductor layer(thicker areas of 12”)(claim 8) fig. 7e; and a pair of second source/drain regions(claim 10) disposed in the semiconductor layer (12”)and spaced from the first source/drain regions, wherein the second source/drain regions are disposed directly over the second lower surface of the semiconductor layer (thicker areas of 12”)claim 10 fig. 7e.
Regarding claim 15, An et al discloses wherein: the first source/drain regions(claim 8) are vertically spaced from the semiconductor substrate (16)a fifth distance fig. 7e; and the second source/drain regions (claim 10)are vertically spaced from the semiconductor substrate(16) a sixth distance different than the fifth distance fig. 7e.
Claim(s) 16 , 19, & 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (US Pub no 2010/0213548 A1).
Regarding claim 16, Chang et al discloses An integrated chip (IC), comprising:
a semiconductor substrate(30) [0028]; an insulating structure (61/39)disposed over the semiconductor substrate(30)[0029], wherein the insulating structure(61/39) comprises a first region(transistor region 210) having a first upper surface(61 /39 of 210) and a second region (transistor region 110)having a second upper surface(61 /39 of 110) below the first upper surface(fig. 3c), the first region (transistor region 210)comprising one or more dielectric materials (61/39)continuously wrapping around one or more filler structures(region 216)[0043][0041] fig. 3c; a semiconductor layer(214) disposed over the insulating structure(61/39)[0043], the semiconductor layer(214) having a first thickness over the first upper surface (61 /39 of 210)and a second thickness over the second upper surface(61 /39 of 110), the first thickness being smaller than the second thickness(fig. 3c)[0046][0029]; a first semiconductor device(210) disposed directly over the first upper surface(61 /39 of 210); and a second semiconductor device(110) disposed directly over the second upper surface. 61 /39 of 110)[0040].
Regarding claim 19, Chang et al discloses wherein the first semiconductor device comprises a first gate structure(212) arranged between first source/drain regions(213) disposed within the semiconductor layer(214)[0040]; and wherein the second semiconductor device(110) comprises a second gate structure(112) arranged
between second source/drain regions (113)disposed within the semiconductor layer(114), the first source/drain regions(113) having a smaller depth than the second source/drain regions(214)(fig. 3c).
Regarding claim 20, Chang et al discloses wherein the one or more filler structures (216) within the first region (transistor region 210)comprise a semiconductor material having a bottommost surface[0041] fig. 3c, the bottommost surface being vertically above a topmost surface of the one or more dielectric materials (61)in the second region(transistor region 110) fig. 3c.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Holt (US Pub no. 2006/0214225 A1) in view of Krishnan US Patent 6,492,209 B1).
Regarding claim 7, Holt et al discloses all the claim limitations of claim 5 and further teach the first source/drain regions extend into the semiconductor layer a third distance; and the second source/drain regions extend into the semiconductor layer a fourth distance but fails to teach a fourth distance different than the third distance.
However, Krishnan et al discloses having a first source/drain regions(104/104-112) a third distance and a second source/drain regions (104/106-114)extend a fourth distance different than the third distance(column 4 lines 60-61). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Holt et al with the teachings of Krishnan et al to reduce threshold voltage shifts.
Regarding claim 8, Krishnan et al discloses wherein: the first source/drain regions (104/104-112)extend vertically from an upper surface of the semiconductor layer(60)to the insulating structure(70/94); and the second source/drain regions((104/106-114)extend vertically from the upper surface of the semiconductor layer (60) to the insulating structure(70/94) (col. 4, lines 45-62)
Regarding claim 9, Krishnan et al discloses wherein: the first source/drain regions(104/104-112) extend vertically from an upper surface of the semiconductor layer to the insulating structure(70/94); the second source/drain regions(104/104-114) extend vertically into the semiconductor layer (60)from the upper surface of the semiconductor layer(60); and the second source/drain regions(104/104-114) are vertically spaced from the insulating structure(70/94).
Claim(s) 17 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US Pub no 2010/0213548 A1) in view of Waite (US Pub no 2006/0118918 A1).
Regarding claim 17, Chang et al discloses all the claim limitations of claim 16 and further teaches dielectric layers(61/39) disposed on sidewalls and an upper surface of the one or more filler (116/216) fig. 3c but fails to teach wherein the one or more dielectric materials comprise a first dielectric layer disposed along a lower surface of the one or more filler structures
However, Waite et al discloses a semiconductor device comprising an insulating material (48) isolating a lower surface of a silicon layer (19)[0032][0034] fig. 14-fig. 16. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Chang et al with the teachings of Waite et al such that the one or more dielectric materials comprise a first dielectric layer disposed along a lower surface of the one or more filler structures and a second dielectric layer disposed on sidewalls and an upper surface of the one or more filler structures and further disposed on an upper surface of the first dielectric layer results to provide isolation and improve hole mobility.
Regarding claim 18, Chang et al in view of Waite et al discloses the claim limitations of claim 17.Change et al fails to teach wherein the upper surface of the first dielectric layer contacts a lower surface of the second dielectric layer along an interface that spans an entirety of the second upper surface.
However, Waite et al discloses an upper surface of a dielectric layer (24-48)contacts a lower surface of the second dielectric layer (14-48)along an interface that spans an entirety of the second upper surface[0035].It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Chang et al with the teachings of Waite et al such that wherein the upper surface of the first dielectric layer contacts a lower surface of the second dielectric layer along an interface that spans an entirety of the second upper surface results to provide isolation and improved hole mobility.
Conclusion
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/LATANYA N CRAWFORD EASON/ Primary Examiner, Art Unit 2813
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