DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
2. Claims 1-20 are pending in the application, wherein this application is a divisional application of 17/370,087 filed on 8 July 2021.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 8 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 8, it recites “wherein the additional interconnect conductive structure has a critical dimension that is greater than 0 nanometers and less than about 15 nanometers”. Support cannot be found in the specification for claiming anything between 0 nanometers and 5 nanometers. For example, ¶0034 of the instant specification only supports a critical dimension for the small conductive structure of “between 5 and 20 nanometers”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-7, 9-11, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsiang-Wei Liu et al. (US 20160005691 A1; hereinafter Liu).
Regarding Claim 1, Liu discloses an integrated chip (Fig. 2; 200; ¶0020), comprising:
a first interconnect dielectric layer (108a; ¶0020) arranged over a substrate (102; ¶0020);
a second interconnect dielectric layer (108b; ¶0020) arranged over the first interconnect dielectric layer (108a); and
an interconnect conductive structure (114b/208b; wherein 114b is one of the plurality of 114’s and 208b is one of the plurality of 208’s) arranged within the second interconnect dielectric layer and comprising:
an outer portion (208b) comprising a first conductive material (¶0021; cobalt (Co)), and
a central portion (114b) comprising a second conductive material (material of 114 is copper (Cu); ¶0016) that is different than the first conductive material (materials of 114 and 208 are different), wherein outermost sidewalls of the central portion (sidewalls of 114b) are laterally surrounded by the outer portion (208b) (as shown in Fig. 2).
Regarding Claim 2, Liu discloses the integrated chip of claim 1, wherein the interconnect conductive structure (114b/208b) has a critical dimension greater than about 15 nanometers (114 is greater than 30nm; ¶0015).
Regarding Claim 3, Liu discloses the integrated chip of claim 1, wherein the second conductive material comprises copper (material of 114 is Cu; ¶0016).
Regarding Claim 6, Liu discloses the integrated chip of claim 1, further comprising: an additional interconnect conductive structure (112b) arranged laterally beside the interconnect conductive structure (114b/208b), arranged within the second interconnect dielectric layer (208b), and comprising the first conductive material (112 comprises Co; ¶0016).
Regarding Claim 7, Liu discloses the integrated chip of claim 6, wherein the additional interconnect conductive structure (112b) has a smaller critical dimension than the interconnect conductive structure (114b/208b) (as shown in Fig. 2 and ¶0015).
Regarding Claim 9, Liu discloses an integrated chip (Fig. 2; 200; ¶0020), comprising:
an interconnect dielectric layer (108b; ¶0020) arranged over a substrate (102; ¶0020);
a first interconnect conductive structure (112b; wherein 112b is one of the plurality of 112’s; ¶0015) arranged within the interconnect dielectric layer (108b) and comprising a first conductive material; and
a second interconnect conductive structure (114b/208b; wherein 114b is one of the plurality of 114’s and 208b is one of the plurality of 208’s) arranged within the interconnect dielectric layer (108b), arranged laterally beside the first interconnect conductive structure (112b), and comprising:
an outer portion (208b) comprising the first conductive material (¶0021; cobalt (Co)), and
a central portion (114b) comprising a second conductive material (material of 114 is copper (Cu); ¶0016) that is different than the first conductive material (Co and Cu are different), wherein outermost sidewalls of the central portion (114b) are laterally surrounded by the outer portion (208b) (as shown in Fig. 2).
Regarding Claim 10, Liu discloses the integrated chip of claim 9, wherein the second interconnect conductive structure (114b/208b) has outermost sidewalls that directly contact the interconnect dielectric layer (108b) (as shown in Fig. 2).
Regarding Claim 11, Liu discloses the integrated chip of claim 9, wherein the second interconnect conductive structure (114b/208b) has a greater critical dimension than the first interconnect conductive structure (112b) (as shown in Fig. 2 and ¶0015).
Regarding Claim 14, Liu discloses the integrated chip of claim 9, wherein the second conductive material comprises copper (material of the plurality of 114’s is Cu; ¶0016).
Claims 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Teng-Yen Huang (US 20220181260 A1; hereinafter Huang).
Regarding Claim 17, Huang discloses an integrated chip (Fig. 1; 100), comprising:
an interconnect dielectric layer (105; ¶0039) arranged over a substrate (101; ¶0039);
a first interconnect structure (123a; ¶0040) arranged within the interconnect dielectric layer (105) and having a first width (as shown in Fig. 1 in view of Fig. 9; W1), wherein the first interconnect structure (123a) comprises a first conductive material (CuMn; ¶0046-¶0047);
a second interconnect structure (127/123; ¶0046-¶0047) arranged within the interconnect dielectric layer (105) and having a second width (as shown in Fig. 1 in view of Fig. 9; W2) that is larger than the first width (W1) (as shown in Fig. 1 in view of Fig. 9; ¶0060), wherein the second interconnect structure (127/123) comprises a second conductive material (material of 123; CuMn; ¶0046-¶0047) along outermost sidewalls of the second interconnect structure (Fig. 1) and a third conductive material (material of 127; Cu; ¶0047) between interior sidewalls of the second conductive material that face one another (as shown in Fig. 1); and
wherein the second conductive material (of 123) physically contacts the third conductive material (of 127) along an interface that vertically extends from a bottommost surface of the second conductive material to a topmost surface of the second conductive material (as shown in Fig. 1).
Regarding Claim 18, Huang discloses the integrated chip of claim 17, wherein the first conductive material (of 123a) continuously and laterally extends between opposing outermost sidewalls of the first interconnect structure (123a) through a vertical center of the first interconnect structure (123a) (as shown in Fig. 1).
Regarding Claim 19, Huang discloses the integrated chip of claim 17, wherein the third conductive material (of 127) vertically extends completely through the second conductive material (of 123) within the second interconnect structure (as shown in Fig. 1).
Regarding Claim 20, Huang discloses the integrated chip of claim 17, wherein the first conductive material (of 123a; CuMn) and the second conductive material (of 123; CuMn) are a same material (¶0047).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiang-Wei Liu et al. (US 20160005691 A1; hereinafter Liu).
Regarding Claim 8, Liu discloses the integrated chip of claim 6, wherein the additional interconnect conductive structure has a critical dimension that is greater than 0 nanometers and less than about 15 nanometers (Liu discloses 112 has a width between 3nm and 30nm; ¶0015).
Although the range of Liu substantially overlaps the claimed range, the ranges are not identical. However, Liu discloses in ¶0009-¶0011 that as the sizes of ICs are scaled downward, the different metals used throughout Liu for the small conductive structures are suitable to fill gaps smaller than 30nm, specifically between 3nm-30nm (¶0015).
Absent evidence of criticality, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the critical dimension of Liu to be in the smaller claimed range in order to support Liu’s acknowledged downscaling of integrated chip components. MPEP 2144.05
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiang-Wei Liu et al. (US 20160005691 A1; hereinafter Liu) in view of Chenglong Zhang et al. (US 20160111368 A1; hereinafter Zhang).
Regarding Claim 4, Liu discloses the integrated chip of claim 1, but does not expressly disclose wherein a topmost surface of the interconnect conductive structure has a smaller width than a bottommost surface of the interconnect conductive structure.
In the same field of endeavor, Zhang teaches various interconnect structures (Fig. 10; 203 or 209; ¶0064) that may be formed in shapes with tapered sidewalls, resulting in the uppermost surface having a smaller width than a bottom most surface (as in 203) or a uppermost surface having a larger width than a bottom most surface (as in 209) depending on the desired formation method (Fig. 5-Fig. 6 where the metal is patterned first or Fig. 8-Fig. 9 where the metal is filled in holes).
The Applicant has not presented persuasive evidence that the claimed shape is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed shape). Also, the Applicant has not shown that the claimed shape produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. It has been held that is not inventive by change the shape in view of In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Thus, absent unexpected results, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the claimed shape to the interconnect structure of Liu since Zhang shows various differently shaped interconnects are suitable alternative shapes for the purpose of an electrical interconnect in a semiconductor device.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hsiang-Wei Liu et al. (US 20160005691 A1; hereinafter Liu) in view of Soo Doo Chae et al. (US 20180350665 A1; hereinafter Chae).
Regarding Claim 5, Liu discloses the integrated chip of claim 1, but does not expressly disclose further comprising:
a spacer structure arranged directly over the outer portion of the interconnect conductive structure, wherein the spacer structure has a topmost surface that is substantially coplanar with topmost surfaces of the central portion of the interconnect conductive structure and the second interconnect dielectric layer.
In the same field of endeavor, Chae teaches an interconnect conductive structure (Fig. 4F; 206/208/210/212) arranged in a dielectric layer (200; ¶0024) comprising an outer portion (208) comprising a first conductive material (¶0027; Ru; equivalent to the Co of Liu as disclosed in Liu ¶0021), and
a central portion (212) comprising a second conductive material (¶0028; Cu; same as in Liu) that is different than the first conductive material (Ru and Cu are different), wherein outermost sidewalls of the central portion (sidewalls of 212) are laterally surrounded by the outer portion (208) (as shown in Fig. 4F);
further comprising: a spacer structure (210, which spaces 208 from 212) arranged directly over the outer portion (210 is directly over 208) of the interconnect conductive structure, wherein the spacer structure (210) has a topmost surface that is substantially coplanar with topmost surfaces of the central portion (212) of the interconnect conductive structure and the dielectric layer (200) (as shown in Fig. 4F).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the spacer configuration of Chae in the structure of Liu to act as a diffusion barrier (Chae; ¶0028) between the different metals of the interconnect structure.
Regarding Claim 15, Liu discloses the integrated chip of claim 9, but does not expressly disclose further comprising:
a spacer structure arranged directly over the outer portion of the second interconnect conductive structure, wherein the spacer structure has topmost surfaces that are substantially coplanar with topmost surfaces of the central portion of the second interconnect conductive structure and the interconnect dielectric layer.
In the same field of endeavor, Chae teaches an interconnect conductive structure (Fig. 4F; 206/208/210/212) arranged in a dielectric layer (200; ¶0024) comprising an outer portion (208) comprising a first conductive material (¶0027; Ru; equivalent to the Co of Liu as disclosed in Liu ¶0021), and
a central portion (212) comprising a second conductive material (¶0028; Cu; same as in Liu) that is different than the first conductive material (Ru and Cu are different), wherein outermost sidewalls of the central portion (sidewalls of 212) are laterally surrounded by the outer portion (208) (as shown in Fig. 4F);
further comprising: a spacer structure (210, which spaces 208 from 212) arranged directly over the outer portion (210 is directly over 208) of the interconnect conductive structure, wherein the spacer structure (210) has topmost surfaces that are substantially coplanar with topmost surfaces of the central portion (212) of the interconnect conductive structure and the dielectric layer (200) (as shown in Fig. 4F).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the spacer configuration of Chae in the second interconnect conductive structure of Liu to act as a diffusion barrier (Chae; ¶0028) between the different metals of the interconnect structure.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiang-Wei Liu et al. (US 20160005691 A1; hereinafter Liu) in view of Shih-Kang Fu et al. (US 20170194201 A1; hereinafter Fu)
Regarding Claim 12, Liu discloses the integrated chip of claim 9, but does not expressly disclose wherein a topmost surface of the central portion of the second interconnect conductive structure is above a topmost surface of the outer portion of the second interconnect conductive structure.
In the same field of endeavor, Fu teaches a conductive interconnect structure (Fig. 1G) in a dielectric layer (106; ¶0024) comprising an outer portion (112; ¶0026) with a different material than and surrounding an inner portion (116; ¶0030), wherein a topmost surface of the central portion (top of 116) of the interconnect conductive structure is above a topmost surface of the outer portion (top of 112) of the interconnect conductive structure.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the features of Fu for the second interconnect conductive structure of Liu in order to provide a greater contact surface for connecting with other conductive features or to compensate for defects (Fu; ¶0043).
Allowable Subject Matter
Claims 13 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 13, Liu discloses the integrated chip of claim 9. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein a topmost surface of the second interconnect conductive structure has a smaller width than a bottommost surface of the second interconnect conductive structure, and wherein a topmost surface of the central portion of the second interconnect conductive structure has a larger with than a bottommost surface of the central portion of the second interconnect conductive structure.
The prior art of record does not teach the particular relationship of these shapes wherein the central portion has a wider top surface and narrower bottom surface, while the outer portions simultaneously have narrow top surfaces and wider bottom surfaces resulting in the claimed relationship.
Regarding Claim 16, modified Liu discloses the integrated chip of claim 15. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein the spacer structure is arranged directly over a topmost surface of the first interconnect conductive structure. As shown in Chae, the spacer structure is not simultaneously arranged directly over a topmost surface of the first interconnect conductive structure.
Conclusion
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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