DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-5 and 7-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,532,748 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1-5 and 7-14 are anticipated by claims 1-20 of the patent, and it is not patentably distinct from claims 1-20 of the patent. See the Table as shown below:
Under Examination Claims
Patented Claims
1. A method comprising:
forming a first dielectric layer over a substrate, the first dielectric layer having a first recess;
forming a conductive layer in the first recess and over an upper surface of the first dielectric layer;
planarizing the conductive layer to form a conductive feature in the first recess, the conductive feature having a second recess;
cleaning the conductive feature and the first dielectric layer, the conductive feature having carbon-containing residue after the cleaning, the cleaning enlarging the second recess;
removing at least a portion of the carbon-containing residue from the conductive feature; and
forming a second dielectric layer over the conductive feature, wherein the second dielectric layer extends into the second recess.
Anticipated by Patented claims 15 and 17:
15. A method comprising:
forming a dielectric layer over a substrate, the dielectric layer having a recess extending through the dielectric layer; forming a gate electrode layer in the recess and over a top surface of the dielectric layer, the gate electrode layer having a void within the recess; performing a planarization process on the gate electrode layer to expose the top surface of the dielectric layer, wherein the planarization process opens the void and forms first residues in the void and second residues within the gate electrode layer;
performing a cleaning process on the gate electrode layer to remove the first residues, wherein the cleaning process further removes a first portion of the gate electrode layer and reduces a depth of the void;
implanting hydrogen atoms into the gate electrode layer and the dielectric layer, wherein the hydrogen atoms react with the second residues to form a volatile compound;
performing an etch process on the gate electrode layer to remove a second portion of the gate electrode layer and further reduce the depth of the void; and forming a cap layer over a remaining portion of the gate electrode layer, wherein the cap layer fills a remaining portion of the void (as patented in claim 15);
17. The method of claim 15, wherein the second residues comprise carbon and the volatile compound comprises a gaseous hydrocarbon compound (as patented in claim 17).
Note: the patented claim limitation of gate electrode layer is equivalent to the claimed limitation of “conductive feature,” the patented claim limitation of etch process is equivalent to the claimed limitation of “removing,” and the patented claim limitation of cap layer is equivalent to the claimed limitation of “second dielectric layer.”
2. The method of claim 1, wherein the cleaning recesses the conductive feature.
Anticipated by Patented claim 15:
15. A method comprising:
“the gate electrode layer having a void within the recess;”
“performing an etch process on the gate electrode layer to remove a second portion of the gate electrode layer and further reduce the depth of the void;”
Note: the patented claim limitation of reduce the depth of the void is equivalent to the claimed limitation of “recesses the conductive feature.”
3. The method of claim 1, wherein removing at least a portion of the carbon-containing residue comprises: performing a plasma process using a first process gas, wherein the first process gas reacts with the carbon-containing residue to form a gaseous compound.
Anticipated by Patented claims 15, 17, and 19:
15. A method comprising:
implanting hydrogen atoms (first process gas) into the gate electrode layer and the dielectric layer, wherein the hydrogen atoms react with the second residues to form a volatile (gaseous) compound (as patented in claim 15);
17. The method of claim 15, wherein the second residues comprise carbon and the volatile compound comprises a gaseous hydrocarbon compound (as patented in claim 17);
19. The method of claim 15, wherein implanting the hydrogen atoms into the gate electrode layer and the dielectric layer comprises performing a hydrogen-containing plasma process ((as patented in claim 19).
4. The method of claim 3, wherein the first process gas comprises hydrogen.
Anticipated by Patented claims 15, 17, and 19:
15. A method comprising:
implanting hydrogen atoms (first process gas) into the gate electrode layer and the dielectric layer, wherein the hydrogen atoms react with the second residues to form a volatile (gaseous) compound (as patented in claim 15);
17. The method of claim 15, wherein the second residues comprise carbon and the volatile compound comprises a gaseous hydrocarbon compound (as patented in claim 17);
19. The method of claim 15, wherein implanting the hydrogen atoms into the gate electrode layer and the dielectric layer comprises performing a hydrogen-containing plasma process ((as patented in claim 19).
5. The method of claim 4, wherein the plasma process implants hydrogen into an upper portion of the first dielectric layer.
Anticipated by Patented claims 15, 17, and 19:
15. A method comprising:
implanting hydrogen atoms (first process gas) into the gate electrode layer and the dielectric layer, wherein the hydrogen atoms react with the second residues to form a volatile (gaseous) compound (as patented in claim 15);
17. The method of claim 15, wherein the second residues comprise carbon and the volatile compound comprises a gaseous hydrocarbon compound (as patented in claim 17);
19. The method of claim 15, wherein implanting the hydrogen atoms into the gate electrode layer and the dielectric layer comprises performing a hydrogen-containing plasma process ((as patented in claim 19).
7. The method of claim 3, wherein the gaseous compound comprises CH4.
Anticipated by Patented claim 17:
17. The method of claim 15, wherein the second residues comprise carbon and the volatile compound comprises a gaseous hydrocarbon compound.
8. The method of claim 1, wherein prior to planarizing the conductive layer has a void, wherein planarizing exposes the void to form the second recess.
Anticipated by Patented claim 15:
15. A method comprising:
performing a planarization process on the gate electrode layer to expose the top surface of the dielectric layer, wherein the planarization process opens the void and forms first residues in the void and second residues within the gate electrode layer;
9. A method comprising:
forming a dielectric layer over a substrate, the dielectric layer having a first recess;
forming a conductive layer in the first recess, the conductive layer having a void;
polishing the conductive layer to form a conductive feature in the first recess, the polishing exposing the void to form a second recess in the conductive feature, wherein after polishing an upper portion of the conductive layer comprises residues; and
implanting hydrogen atoms into the conductive feature and the dielectric layer, wherein implanting hydrogen reduces the residues in the conductive feature.
Anticipated by Patented claim 15:
15. A method comprising:
forming a dielectric layer over a substrate, the dielectric layer having a recess extending through the dielectric layer; forming a gate electrode layer in the recess and over a top surface of the dielectric layer, the gate electrode layer having a void within the recess; performing a planarization process on the gate electrode layer to expose the top surface of the dielectric layer, wherein the planarization process opens the void and forms first residues in the void and second residues within the gate electrode layer;
performing a cleaning process on the gate electrode layer to remove the first residues, wherein the cleaning process further removes a first portion of the gate electrode layer and reduces a depth of the void;
implanting hydrogen atoms into the gate electrode layer and the dielectric layer, wherein the hydrogen atoms react with the second residues to form a volatile compound;
performing an etch process on the gate electrode layer to remove a second portion of the gate electrode layer and further reduce the depth of the void; and forming a cap layer over a remaining portion of the gate electrode layer, wherein the cap layer fills a remaining portion of the void.
Note: the patented claim limitation of gate electrode layer is equivalent to the claimed limitation of “conductive layer” and the patented claim limitation of planarization is equivalent to the claimed limitation of “polishing.”
10. The method of claim 9, further comprising: after implanting hydrogen atoms, recessing the conductive feature; and depositing an insulating material over the conductive feature, the insulating material filling the second recess.
Anticipated by Patented claim 15:
15. A method comprising:
implanting hydrogen atoms into the gate electrode layer and the dielectric layer, wherein the hydrogen atoms react with the second residues to form a volatile compound;
performing an etch process on the gate electrode layer to remove a second portion of the gate electrode layer and further reduce the depth of the void; and forming a cap layer over a remaining portion of the gate electrode layer, wherein the cap layer fills a remaining portion of the void.
Note: the patented claim limitation of etch process is equivalent to the claimed limitation of “recessing” and the patented claim limitation of cap layer is equivalent to the claimed limitation of “insulating material.”
11. The method of claim 10, wherein the recessing reduces a depth of the second recess.
Anticipated by Patented claim 15:
15. A method comprising:
performing an etch process on the gate electrode layer to remove a second portion of the gate electrode layer and further reduce the depth of the void; and forming a cap layer over a remaining portion of the gate electrode layer, wherein the cap layer fills a remaining portion of the void.
Note: the patented claim limitation of etch process is equivalent to the claimed limitation of “recessing” and the patented claim limitation of reduce the depth of the void is equivalent to the claimed limitation of “reduces a depth of the second recess.”
12. The method of claim 9, wherein implanting further implants nitrogen atoms into the dielectric layer.
Anticipated by Patented claim 20:
20. The method for forming a semiconductor device structure as claimed in claim 16, wherein a process gas used by the hydrogen-containing plasma process comprises hydrogen and nitrogen, and the first hydrogen-containing portion contains hydrogen atoms and nitrogen atoms.
13. The method of claim 9, further comprising: prior to implanting hydrogen, recessing the conductive feature in the first recess.
Anticipated by Patented claim 15:
15. A method comprising:
performing a cleaning process on the gate electrode layer to remove the first residues, wherein the cleaning process further removes a first portion of the gate electrode layer and reduces a depth of the void;
Note: the patented claim limitation of cleaning process is equivalent to the claimed limitation of “recessing.”
14. The method of claim 9, wherein implanting hydrogen reduces a carbon content in the conductive feature.
Anticipated by Patented claim 15:
implanting hydrogen atoms into the gate electrode layer and the dielectric layer, wherein the hydrogen atoms react with the second residues to form a volatile compound;
Note: patented claim limitation of hydrogen atoms react with the second residues to form a volatile compound is equivalent to the claimed limitation of “reduces a carbon content in the conductive feature.”
Allowable Subject Matter
Claims 6, 17-18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein a lower portion of the first dielectric layer remains free of implanted hydrogen,” as recited in claim 6.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “prior to performing the hydrogen-containing plasma process, recessing the conductive feature, wherein recessing the conductive feature widens the first recess; and after performing the hydrogen-containing plasma process, removing upper portions of the conductive feature and the dielectric layer,” as recited in claim 17.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein performing the hydrogen-containing plasma process reduces carbon residue,” as recited in claim 20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9, 15-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (U.S. 2010/0065926 A1, hereinafter refer to Yeh) in view of Koldiaev et al. (U.S. 2005/0255684 A1, hereinafter refer to Koldiaev).
Regarding Claim 9: Yeh discloses a method (see Yeh, Figs.4-5 as shown below and ¶ [0002]) comprising:
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forming a dielectric layer (122) over a substrate (102), the dielectric layer (122) having a first recess (see Yeh, Fig.4 as shown above);
forming a conductive layer (402/406) in the first recess, the conductive layer (402/406) having a void (see Yeh, Fig.4 as shown above);
polishing the conductive layer (402/406) to form a conductive feature in the first recess, the polishing exposing the void (408) to form a second recess in the conductive feature, wherein after polishing an upper portion of the conductive layer (402/406) comprises residues (note: it is generally true that the chemical mechanical polished (CMP) conductive surface to have a residues from chemical oxidation and mechanical abrasion process) (see Yeh, Fig.5 as shown above and ¶ [0026]).
Yeh is silent upon explicitly disclosing wherein implanting hydrogen atoms into the conductive feature and the dielectric layer.
For support see Koldiaev, which teaches wherein implanting hydrogen atoms (148/150) into the conductive feature (106) and the dielectric layer (144) (see Koldiaev, Figs.7-8 as shown below and ¶ [0001]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yeh and Koldiaev to enable implanting hydrogen atoms into the conductive feature and the dielectric layer of Yeh as taught by Koldiaev in order to enhance the performance and reliability of semiconductor devices.
The combination of Yeh and Koldiaev is silent upon explicitly disclosing wherein implanting hydrogen reduces the residues in the conductive feature.
However, practicing the combination of Yeh and Koldiaev to implant hydrogen atoms into the conductive feature and the dielectric layer of Yeh as taught by Koldiaev necessarily results the claimed limitation of “implanting hydrogen reduces the residues in the conductive feature” as now specified in claim 9.
Regarding Claim 15: Yeh as modified teaches a method as set forth in claim 9 above. The combination of Yeh and Koldiaev further teaches wherein the hydrogen atoms (148) extend lower in the conductive feature (106) than in the dielectric layer (144) (see Koldiaev, Fig.9 as shown above).
Regarding Claim 16: Yeh discloses a method (see Yeh, Figs.4-5 as shown above and ¶ [0002]) comprising:
forming a dielectric layer (122) over a substrate (102), wherein the dielectric layer (122) has a trench (see Yeh, Fig.4 as shown above);
forming a conductive feature in the trench, wherein an upper surface of the conductive feature having a first recess (408) (see Yeh, Fig.5 as shown above).
Yeh is silent upon explicitly disclosing wherein performing a hydrogen-containing plasma process to implant hydrogen atoms in the conductive feature and the dielectric layer, wherein the hydrogen atoms extend lower in the conductive feature than in the dielectric layer.
For support see Koldiaev, which teaches wherein performing a hydrogen-containing plasma process to implant hydrogen atoms in the conductive feature (106) and the dielectric layer (144), wherein the hydrogen atoms (148) extend lower in the conductive feature (106) than in the dielectric layer (144) (see Koldiaev, Figs.7-9 as shown above, ¶ [0001], and ¶ [0047]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yeh and Koldiaev to enable performing a hydrogen-containing plasma process to implant hydrogen atoms in the conductive feature and the dielectric layer of Yeh, wherein the hydrogen atoms extend lower in the conductive feature than in the dielectric layeras taught by Koldiaev in order to enhance the performance and reliability of semiconductor devices.
Regarding Claim 19: Yeh as modified teaches a method as set forth in claim 16 above. The combination of Yeh and Koldiaev further teaches wherein a bottom portion of the conductive feature (106) remains free of implanted hydrogen (146) (see Koldiaev, Fig.8 as shown above).
Conclusion
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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