Prosecution Insights
Last updated: August 17, 2026
Application No. 18/776,416

3DIC STRUCTURE FOR HIGH VOLTAGE DEVICE ON A SOI SUBSTRATE

Non-Final OA §112
Filed
Jul 18, 2024
Priority
Jun 24, 2021 — provisional 63/214,406 +1 more
Examiner
GEBREMARIAM, SAMUEL A
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
697 granted / 838 resolved
+23.2% vs TC avg
Moderate +8% lift
Without
With
+8.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
19 currently pending
Career history
855
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
38.3%
-1.7% vs TC avg
§102
28.4%
-11.6% vs TC avg
§112
22.5%
-17.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 838 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 21-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The limitation “the first through via is directly between and borders the pair of DTI structures, and wherein semiconductor material of the device semiconductor layer is continuous from the second semiconductor device to the second through via” as recited in claim 21 does not have support in the specification as originally filed. Allowable Subject Matter Claims 1-15 are allowed. Reason for indicating allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination at least the limitation “portions of the first DTI structure are spaced apart from portions of the second DTI structure by the active layer of the SOI substrate; and a through substrate via (TSV) extending completely through the SOI substrate from a second side to the first side of the SOI substrate, wherein the TSV is arranged directly between the first DTI structure and the second DTI structure, and wherein the TSV is coupled to the interconnect structure” as recited in claim 1 is the first major difference between the prior art and the claimed invention and the second major difference is the limitation “a through substrate via (TSV) extending through the STI structure and the SOI substrate from the second side of the SOI substrate to the first side of the SOI substrate and coupling the bond pad structure to the first interconnect structure; deep trench isolation (DTI) structures extending through the active layer of the SOI substrate and surrounding the TSV” as recited in claim 9. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Jul 18, 2024
Application Filed
Sep 25, 2024
Response after Non-Final Action
Jul 28, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12701982
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
2y 9m to grant Granted Aug 04, 2026
Patent 12696440
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
3y 4m to grant Granted Jul 28, 2026
Patent 12696691
RESISTIVE RANDOM-ACCESS MEMORY (RRAM) DEVICES WITH INTERFACE LAYERS
3y 1m to grant Granted Jul 28, 2026
Patent 12696547
TRANSFORMER DEVICE AND SEMICONDUCTOR DEVICE
3y 1m to grant Granted Jul 28, 2026
Patent 12696644
DISPLAY SUBSTRATE, MANUFACTURING METHOD, AND DISPLAY DEVICE
2y 6m to grant Granted Jul 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
91%
With Interview (+8.0%)
2y 9m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 838 resolved cases by this examiner. Grant probability derived from career allowance rate.

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