Prosecution Insights
Last updated: October 01, 2026
Application No. 18/776,441

ENGINEERING METAL OXIDE LAYER INTERFACES TO IMPROVE ELECTRONIC DEVICE STABILITY

Non-Final OA §102§103
Filed
Jul 18, 2024
Priority
Jul 25, 2023 — provisional 63/528,688
Examiner
INOUSSA, MOULOUCOULAY
Art Unit
Tech Center
Assignee
Applied Materials Inc.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
676 granted / 790 resolved
+25.6% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
25 currently pending
Career history
801
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
44.3%
+4.3% vs TC avg
§102
38.0%
-2.0% vs TC avg
§112
15.1%
-24.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 790 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-10, 13-16, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (US 2022/0149201 A1). With respect to claim 1, Yamazaki discloses, in Figs.1A-57B, a transistor device (100) comprising: a base structure (102); and a metal oxide layer (108) disposed on the base structure (102) (see, for example, Par.[0250] wherein the transistor 100 is provided over a substrate 102 and includes the insulating layer 103, the semiconductor layer 108, the insulating layer 110, the metal oxide layer 114, the conductive layer 112, an insulating layer 118, and the like; see Par.[0225] wherein It is possible to use the metal oxide film can be used as the semiconductor layer 108 for the semiconductor layer 108; the semiconductor layer 108a can be formed using a metal oxide film that has a higher atomic ratio of the element M than the semiconductor layer 108b), the metal oxide layer comprising at least one region having a gradient profile with respect to oxygen (O2) composition (see Par.[0349] wherein at the time of depositing the metal oxide film (i.e.; at most deposition of the entire region metal oxide 114), the amount of oxygen supplied into the insulating layer 110 can be increased with a higher proportion (i.e.; higher percentage) of the oxygen flow rate to the total flow rate of the deposition gas introduced into a deposition chamber of a deposition apparatus (a higher oxygen flow rate ratio) or with higher oxygen partial pressure in the deposition chamber; the oxygen flow rate ratio or the oxygen partial pressure is, for example, higher than or equal to 50% and lower than or equal to 100%, preferably higher than or equal to 65% and lower than or equal to 100%, further preferably higher than or equal to 80% and lower than or equal to 100%, still further preferably higher than or equal to 90% and lower than or equal to 100%; see Tables 1, 3-4, Par.[0591], [0607], [0619] wherein during deposition deliberated controlled variation in a physical parameters composition metal oxide such as target, temperature, pressure and power with respect to oxygen (O2) composition at argon inert gas are shown; it is submitted gradient profile is the deliberated controlled variation in a physical parameters composition metal oxide). With respect to claim 2, Yamazaki discloses, in Figs.1A-57B, the transistor device, wherein the metal oxide layer (108) is disposed on a buffer layer (103) of the base structure (102) (see Par.[0250]-[0251] wherein the transistor 100 is provided over a substrate 102 and includes the insulating layer 103, the semiconductor layer 108, the insulating layer 110, the metal oxide layer 114, the conductive layer 112, an insulating layer 118, and the like; the semiconductor layer 108 having an island shape is provided over the insulating layer 103). With respect to claim 3, Yamazaki discloses, in Figs.1A-57B, the transistor device, wherein the at least one region comprises an interfacial region/(lower surface region) comprising an interface between the base structure (102) and the metal oxide layer (108) (see, for example, Fig.8B). With respect to claim 4, Yamazaki discloses, in Figs.1A-57B, the transistor device, wherein the metal oxide layer (108) corresponds to a channel region of a transistor (see Par.[0198]-[0199] wherein the semiconductor layer 108 overlapping with the conductive layer 112 functions as a channel formation region). With respect to claim 5, Yamazaki discloses, in Figs.1A-57B, the transistor device, further comprising: a gate dielectric (110) disposed on the metal oxide layer (108); and a gate conductor (112) disposed on the gate dielectric (110) (see Par.[0253] wherein the conductive layer 112 functions as a gate electrode; the insulating layer 110 functions as a gate insulating layer). With respect to claim 6, Yamazaki discloses, in Figs.1A-57B, the transistor device, wherein the at least one region comprises an interfacial region/(upper surface region) comprising an interface between the gate dielectric (110) and the metal oxide layer (108) (see Fig.8B). With respect to claim 7, Yamazaki discloses, in Figs.1A-57B, the transistor device, wherein the metal oxide layer (108) further corresponds to a pair of source/drain regions (108n) (see Par.[0263]-[0265] wherein the low-resistance region 108n functions as a source region or a drain region of the transistor 100). With respect to claim 8, Yamazaki discloses, in Figs.1A-57B, a method comprising: obtaining a base structure (102) of a transistor device (100) (see, for example, Par.[0250] wherein the transistor 100 is provided over a substrate 102 and includes the insulating layer 103, the semiconductor layer 108, the insulating layer 110, the metal oxide layer 114, the conductive layer 112, an insulating layer 118, and the like; see Par.[0225] wherein It is possible to use the metal oxide film can be used as the semiconductor layer 108 for the semiconductor layer 108; the semiconductor layer 108a can be formed using a metal oxide film that has a higher atomic ratio of the element M than the semiconductor layer 108b); and forming, on the base structure (102) using a gas mixture comprising oxygen (O2), a metal oxide layer (108) comprising at least one region having a gradient profile with respect to O2 composition (see Par.[0349] wherein at the time of depositing the metal oxide film (i.e.; at most deposition of the entire region metal oxide 114), the amount of oxygen supplied into the insulating layer 110 can be increased with a higher proportion (i.e.; higher percentage) of the oxygen flow rate to the total flow rate of the deposition gas introduced into a deposition chamber of a deposition apparatus (a higher oxygen flow rate ratio) or with higher oxygen partial pressure in the deposition chamber; the oxygen flow rate ratio or the oxygen partial pressure is, for example, higher than or equal to 50% and lower than or equal to 100%, preferably higher than or equal to 65% and lower than or equal to 100%, further preferably higher than or equal to 80% and lower than or equal to 100%, still further preferably higher than or equal to 90% and lower than or equal to 100%; see Tables 1, 3-4, Par.[0591], [0607], [0619] wherein during deposition deliberated controlled variation in a physical parameters composition metal oxide such as target, temperature, pressure and power with respect to oxygen (O2) composition at argon inert gas are shown; it is submitted gradient profile is the deliberated controlled variation in a physical parameters composition metal oxide). With respect to claim 9, Yamazaki discloses, in Figs.1A-57B, the method, wherein the metal oxide layer (108) is formed on a buffer layer (103) of the base structure (102) (see Par.[0250]-[0251] wherein the transistor 100 is provided over a substrate 102 and includes the insulating layer 103, the semiconductor layer 108, the insulating layer 110, the metal oxide layer 114, the conductive layer 112, an insulating layer 118, and the like; the semiconductor layer 108 having an island shape is provided over the insulating layer 103). With respect to claim 10, Yamazaki discloses, in Figs.1A-57B, the method, wherein the at least one region having a gradient profile with respect to O2 composition comprises an interfacial region comprising an interface between the base structure (102) and the metal oxide layer (108) (see Fig.8B). With respect to claim 13, Yamazaki discloses, in Figs.1A-57B, the method, wherein forming the metal oxide layer comprises: initiating, at a first time and at a first O2 flow, a deposition process to form the metal oxide layer; performing an anneal process at a second time to form the interfacial region; and forming a bulk region and a second interfacial region of the metal oxide layer (see Par.[0335]-[0336] wherein the temperature of the heat treatment can be typically higher than or equal to 150° C. and lower than the strain point of the substrate, higher than or equal to 200° C. and lower than or equal to 500° C., higher than or equal to 250° C. and lower than or equal to 450° C., or higher than or equal to 300° C. and lower than or equal to 450° C; an electric furnace, an RTA (Rapid Thermal Anneal) apparatus, or the like can be used for the heat treatment; the use of the RTA apparatus can shorten the heat treatment time). With respect to claim 14, Yamazaki discloses, in Figs.1A-57B, the method, further comprising forming a gate dielectric on the metal oxide layer, wherein the at least one region having a gradient profile with respect to O2 composition comprises an interfacial region comprising an interface between the metal oxide layer and the gate dielectric (see Fig.8B). With respect to claim 15, Yamazaki discloses, in Figs.1A-57B, the method, wherein forming the metal oxide layer comprises: forming a portion of a metal oxide layer using a gas mixture having a first O2 flow; and ramping down the first O2 flow to a second O2 flow to form the interfacial region (see Par.[0349] wherein the amount of oxygen supplied into the insulating layer 110 can be increased with a higher proportion of the oxygen flow rate to the total flow rate of the deposition gas introduced into a deposition chamber of a deposition apparatus (a higher oxygen flow rate ratio) or with higher oxygen partial pressure in the deposition chamber; the oxygen flow rate ratio or the oxygen partial pressure is, for example, higher than or equal to 50% and lower than or equal to 100%, preferably higher than or equal to 65% and lower than or equal to 100%, further preferably higher than or equal to 80% and lower than or equal to 100%, still further preferably higher than or equal to 90% and lower than or equal to 100%. It is particularly preferable that the oxygen flow rate ratio be 100% and the oxygen partial pressure in the deposition chamber be as close to 100% as possible). With respect to claim 16, Yamazaki discloses, in Figs.1A-57B, the method, wherein the portion of the metal oxide layer comprises a second interfacial region comprising a second interface between the base structure and the second interfacial region, and a bulk region disposed between the interfacial region and the second interfacial region (see Fig.8B). With respect to claim 18, Yamazaki discloses, in Figs.1A-57B, the method, wherein forming the gate dielectric comprises using a deposition process performed at a target temperature to cause a target dissociation of O2 from the metal oxide layer (see Fig.8B). With respect to claim 19, Yamazaki discloses, in Figs.1A-57B, the method, wherein the deposition process is a chemical vapor deposition (CVD) process (see Par.[0205], [0373], [0376] wherein a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. Examples of the CVD method include a plasma-enhanced chemical vapor deposition (PECVD) method and a thermal CVD method; a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used as an apparatus for generating the plasma). With respect to claim 20, Yamazaki discloses, in Figs.1A-57B, the method, wherein the metal oxide layer is formed using a physical vapor deposition (PVD) process (see Par.[0205], [0373], [0376] wherein a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. Examples of the CVD method include a plasma-enhanced chemical vapor deposition (PECVD) method and a thermal CVD method; a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used as an apparatus for generating the plasma). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 11-12, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Ota et al. (US 2014/0051261 A1 hereinafter referred to as “Ota”). With respect to claim 11, Yamazaki discloses all the claimed limitations of claim 10. However, Yamazaki does not explicitly disclose the limitations of claim 11. Ota discloses, in Figs.1-16, the method, wherein forming the metal oxide layer comprises: initiating, at a first time and at a first O2 flow, a deposition process to form the metal oxide layer; ramping up, from the first time to a second time, the first O2 flow to a second O2 flow to form the interfacial region wherein the second O2 flow is approximately equal to an inert gas flow; and forming a bulk region and a second interfacial region of the metal oxide layer (see Par.[0154]-[0166] wherein metal oxide target forming deposition is disclosed; see Fig.11, Par.[0182]-[0184] wherein graph showing initial phase, ramp up phase and final phase of oxygen gas flow times; see Par.[0095] wherein flow the O.sub.2 gas into the third gas supply tube 232c. The flow rate of the O.sub.2 gas flowing into the third gas supply tube 232c is adjusted by the mass flow controller 241c. The O.sub.2 gas with the flow rate adjusted, is supplied into the processing chamber 201 from the gas supply holes 250c of the third nozzle 249c. The O.sub.2 gas supplied into the processing chamber 201 is thermally activated and is exhausted from the exhaust tube 231. At this time, the thermally activated O.sub.2 gas is supplied to the wafers 200 (supply of the O.sub.2 gas). Simultaneously at this time, the valve 243g is opened, to thereby flow the N.sub.2 gas into the third inert gas supply tube 232g). Yamazaki and Ota are analogous art because they are all directed to a deposition process method of metal oxide layer, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Yamazaki to include Ota because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the oxygen gas flowing steps in Yamazaki by including three phases oxygen gas flow as taught by Ota in order to alternately supply gas at low temperature offered by Ota method thereby providing cost effective method capable of forming an excellent thin film in a low temperature zone. With respect to claim 12, Ota discloses, in Figs.1-16, the method, wherein forming the metal oxide layer comprises: initiating, at a first time and at a first O2 flow, a deposition process to form the metal oxide layer; maintaining the first O2 flow for a period of time defined between the first time and a second time; ramping up, from the second time to a third time, the first O2 flow to a second O2 flow to form the interfacial region, wherein the second O2 flow is approximately equal to an inert gas flow; and forming a bulk region and a second interfacial region of the metal oxide layer (see Par.[0154]-[0166] wherein metal oxide target forming deposition is disclosed; see Fig.11, Par.[0182]-[0184] wherein graph showing initial phase, ramp up phase and final phase of oxygen gas flow times; see Par.[0095] wherein flow the O.sub.2 gas into the third gas supply tube 232c. The flow rate of the O.sub.2 gas flowing into the third gas supply tube 232c is adjusted by the mass flow controller 241c. The O.sub.2 gas with the flow rate adjusted, is supplied into the processing chamber 201 from the gas supply holes 250c of the third nozzle 249c. The O.sub.2 gas supplied into the processing chamber 201 is thermally activated and is exhausted from the exhaust tube 231. At this time, the thermally activated O.sub.2 gas is supplied to the wafers 200 (supply of the O.sub.2 gas). Simultaneously at this time, the valve 243g is opened, to thereby flow the N.sub.2 gas into the third inert gas supply tube 232g). With respect to claim 17, Yamazaki discloses all the claimed limitations of claim 14. However, Yamazaki does not explicitly disclose the limitations of claim 17. Ota discloses, in Figs.1-16, the method, wherein forming the metal oxide layer comprises: forming a portion of a metal oxide layer using a gas mixture having a first O2 flow; and ramping down, from a first time to a second time, the first O2 flow to a second O2 flow; and maintaining the second O2 flow for a period of time defined between the second time and a third time to form the interfacial region (see Par.[0154]-[0166] wherein metal oxide target forming deposition is disclosed; see Fig.11, Par.[0182]-[0184] wherein graph showing initial phase, ramp up phase and final phase of oxygen gas flow times; see Par.[0095] wherein flow the O.sub.2 gas into the third gas supply tube 232c. The flow rate of the O.sub.2 gas flowing into the third gas supply tube 232c is adjusted by the mass flow controller 241c. The O.sub.2 gas with the flow rate adjusted, is supplied into the processing chamber 201 from the gas supply holes 250c of the third nozzle 249c. The O.sub.2 gas supplied into the processing chamber 201 is thermally activated and is exhausted from the exhaust tube 231. At this time, the thermally activated O.sub.2 gas is supplied to the wafers 200 (supply of the O.sub.2 gas). Simultaneously at this time, the valve 243g is opened, to thereby flow the N.sub.2 gas into the third inert gas supply tube 232g). Yamazaki and Ota are analogous art because they are all directed to a deposition process method of metal oxide layer, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Yamazaki to include Ota because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the oxygen gas flowing steps in Yamazaki by including three phases oxygen gas flow as taught by Ota in order to alternately supply gas at low temperature offered by Ota method thereby providing cost effective method capable of forming an excellent thin film in a low temperature zone. Citation of Pertinent Prior Art The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure. Examiner’s Telephone/Fax Contacts Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Jul 18, 2024
Application Filed
Aug 11, 2026
Non-Final Rejection mailed — §102, §103
Sep 22, 2026
Interview Requested

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.2%)
2y 5m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 790 resolved cases by this examiner. Grant probability derived from career allowance rate.

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