DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 17 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 9, 10, 12, 13, and 15 – 17 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Barnard et al. (US 2021/0373585 A1; hereinafter Barnard).
Regarding Claim 1, Barnard discloses a semiconductor device handling apparatus (Fig. 1, item 105) that moves a device under test (DUT) (Fig. 1, item 120) so that a terminal (Fig. 1, terminal of the DUT) on a first surface (Fig. 1, bottom side of item 120) of the DUT (Fig. 1, item 120) contacts a contact part (Fig. 1, item 125) of a semiconductor device testing apparatus (Fig. 1, item 100), the semiconductor device handling apparatus (Fig. 1, item 105) comprising:
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a holding part (Fig. 1, item 110) that holds a second surface (Fig. 1, top side of item 120) of the DUT (Fig. 1, item 120); and
an optical probe (Fig. 1, item 130) that inputs and outputs an optical signal to and from (Fig. 1 and para [0020]; the optical connections 140 can be implemented as fibers that extend from the optical test assembly 130 into the workpress 110, and are turned back towards the topside of the DUT 120) an optical connection part (Fig. 1, by item 140) on the second surface (Fig. 1, top side of item 120) of the DUT (Fig. 1, item 120).
Regarding Claim 9, Barnard discloses the semiconductor device handling apparatus according to claim 1, wherein the optical probe comprises an optical transmission path that transmits the optical signal (para [0021]; an optical transceiver for transmitting and receiving optical signals).
Regarding Claim 10, Barnard discloses the semiconductor device handling apparatus according to claim 1, wherein the holding part (Fig. 1, item 110) comprises: a contact surface (Fig. 1, contact surface of item 110) that contacts the second surface (Fig. 1, top side of item 120) of the DUT (Fig. 1, item 120); and a temperature adjusting mechanism (Fig. 1, item 115) that adjusts a temperature of the DUT (Fig. 1, item 120) via the contact surface (Fig. 1 and para [0020]; air source 115 applies an airflow on the DUT 120 via a directed air channel (e.g., hose, tube, hollow pathway) that extends through the workpress 110).
Regarding Claim 12, Barnard discloses the semiconductor device handling apparatus according to claim 1, comprising a first moving device that moves the holding part relative to the contact part and presses the DUT held by the holding part against the contact part and contact the terminal of the DUT with the contact part (Fig. 1 and para [0020]; a handler 105 (e.g., integrated circuit (IC) handler, chip hander) is a robotic system that can carefully move a device under test (DUT) 120 into position for testing and calibration; a workpress 110 (e.g., a workpress assembly) is attached to the handler 105 to move the DUT 120 to the test socket base 125).
Regarding Claim 13, Barnard discloses the semiconductor device handling apparatus according to claim 1, wherein the DUT (Fig. 1, item 120) comprises a die having (para [0025]; DUT generates different light beams (e.g., at different wavelengths, or on different channels) that output onto one or more of a plurality of fibers (e.g., optical connections 140)) the optical connection part (Fig. 1, item 140).
Regarding Claim 15, Barnard discloses the semiconductor device handling apparatus according to claim 1, wherein the contact part (Fig. 1, item 125) includes a probe card comprising a contactor that contacts the terminal of the DUT (para [0020]; test socket base 125 is further positioned on an optical test assembly 130, which provides optical testing of the DUT 120 using one or more optical analysis modules (e.g., an optical spectrum analyzer, OSA), and an electrical automated test equipment (ATE) 145, which provides electrical automated testing using one or more electrical analyzer modules; the DUT 120 is electrically connected via electrical connections (e.g., high speed socket 125) to the optical test assembly and the ATE).
Regarding Claim 16, Barnard discloses a semiconductor device testing apparatus (Fig. 1, item 100) that tests a device under test (DUT) (Fig. 1, item 120), comprising:
a contact part (Fig. 1, item 125) that inputs and outputs an electrical signal to and from (para [0020]; DUT 120 is electrically connected via electrical connections (e.g., high speed socket 125) to the optical test assembly and the ATE) a terminal on a first surface (Fig. 1, bottom side of item 120) of the DUT (Fig. 1, item 120);
an optical probe (Fig. 1, item 130) that inputs and outputs an optical signal to and from (Fig. 1 and para [0020]; the optical connections 140 can be implemented as fibers that extend from the optical test assembly 130 into the workpress 110, and are turned back towards the topside of the DUT 120) an optical connection part (Fig. 1, by item 140) disposed on a second surface (Fig. 1, top side of item 120) of the DUT (Fig. 1, item 120); and
a testing device (Fig. 1, item 145) connected to the contact part and the optical probe and that transmits the electrical signal and the optical signal, respectively (para [0020]; the test socket base 125 is further positioned on an optical test assembly 130, which provides optical testing of the DUT 120 using one or more optical analysis modules (e.g., an optical spectrum analyzer, OSA), and an electrical automated test equipment (ATE) 145).
Regarding Claim 17, Barnard discloses a semiconductor device testing apparatus (Fig. 1, item 100) that tests a device under test (DUT) (Fig. 1, item 120), comprising:
a semiconductor device handling apparatus (Fig. 1, item 105) that:
moves the DUT (Fig. 1, item 120) so that a terminal (Fig. 1, terminal of the DUT) on a first surface (Fig. 1, bottom side of item 120) of the DUT (Fig. 1, item 120) contacts a contact part (Fig. 1, item 125) of a semiconductor device testing apparatus (Fig. 1, item 100), and comprises:
a holding part (Fig. 1, item 110) that holds a second surface (Fig. 1, top side of item 120) of the DUT (Fig. 1, item 120); and
an optical probe (Fig. 1, item 130) that inputs and outputs an optical signal to and from (Fig. 1 and para [0020]; the optical connections 140 can be implemented as fibers that extend from the optical test assembly 130 into the workpress 110, and are turned back towards the topside of the DUT 120) an optical connection part (Fig. 1, by item 140) on the second surface (Fig. 1, top side of item 120) of the DUT (Fig. 1, item 120); the contact part (Fig. 1, item 125) that inputs and outputs an electrical signal to and from (para [0020]; DUT 120 is electrically connected via electrical connections (e.g., high speed socket 125) to the optical test assembly and the ATE) the terminal disposed (Fig. 1, terminal on bottom side of item 120); and
a testing device (Fig. 1, item 145) connected to the contact part and the optical probe and that transmits the electrical signal and the optical signal, respectively (para [0020]; the test socket base 125 is further positioned on an optical test assembly 130, which provides optical testing of the DUT 120 using one or more optical analysis modules (e.g., an optical spectrum analyzer, OSA), and an electrical automated test equipment (ATE) 145).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Barnard in view of Saito (US 2019/0302178 A1; hereinafter Saito).
Regarding Claim 11, Barnard discloses the semiconductor device handling apparatus according to claim 1, wherein the holding part (Fig. 1, item 110) comprises: a contact surface (Fig. 1, contact surface of item 110) that contacts the second surface (Fig. 1, top side of item 120) of the DUT (Fig. 1, item 120).
But Barnard does not specifically teach a suction holding mechanism that opens to the contact surface and holds the DUT by suction.
However, Saito suggests a suction holding mechanism that opens to the contact surface and holds the DUT by suction (para [0014]; a suction holding mechanism which sucks and holds). 1450
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify Barnard in view of Saito because since both parts are stretched with the suction for the holding operation, it is possible to prevent the slack and wrinkles of both parts even when the outer shape of the DUT is large (Saito, para [0065]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Barnard in view of Wilsher (US 6,781,218 B1; hereinafter Wilsher).
Regarding Claim 14, Barnard discloses the semiconductor device handling apparatus according to claim 13. But Barnard does not specifically teach wherein the DUT comprises a board that has the terminal and on which the die is mounted.
However, Wilsher suggests wherein the DUT (Fig. 5, item 10) comprises a board that has the terminal and on which the die is mounted (column 10, lines 9 – 16; DUT is mounted on board having support ICs (ICs required to make the board/system); workstation is coupled to the input terminals on board and controls the system/board by sending commands via an on-chip (die) scan chain).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify Barnard in view of Wilsher because it would also be advantageous to provide signal outputs to an associated printed circuit board from internal circuit nodes for diagnostic purposes (Wilsher, column 2, lines 37 – 39).
Allowable Subject Matter
Claims 2 – 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 2, the prior art of record does not teach claimed limitation: “further comprising: a first moving device that moves the holding part relative to the contact part and aligns the terminal of the DUT with respect to the contact part; and a second moving device that moves the optical probe relative to the DUT held by the holding part and aligns the optical probe with respect to the optical connection part of the DUT” in combination with all other claimed limitations of claim 2.
Regarding Claims 3 – 8, the claims are allowed as they further limit allowed claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kikuchi et al. (US 2026/0023109 A1) suggests a bridge beam attached to a semiconductor device handling apparatus that handles a semiconductor device, comprising: a beam-shaped main body to which a probe card is attached, wherein the probe card has a contact that is electrically connected to a terminal of the semiconductor device; and a first actuator, attached to the beam-shaped main body, that moves an optical probe relative to the semiconductor device, wherein the optical probe performs one or both of emitting an optical signal to the semiconductor device and receiving the optical signal from the semiconductor device (see claim 1).
Hanai et al. (US 2025/0172609 A1) teaches a probe testing apparatus comprising: a wafer stage including a wafer mounting surface on which a semiconductor wafer is mounted; a temperature sensor including a temperature observation point exposed on the wafer mounting surface and configured to directly measure a temperature of a rear surface of the semiconductor wafer mounted on the wafer mounting surface; a temperature adjustment mechanism configured to adjust a temperature of the wafer stage by heating or cooling the wafer stage; and a controller configured to control the temperature adjustment mechanism in such a manner that a measured temperature by the temperature sensor becomes a target temperature (see claim 1).
Zhuang et al. (US 2022/0397600 A1) discloses a test kit for testing a device under test (DUT), comprising: a socket structure, for containing the DUT; and a plunger assembly detachably coupled with the socket structure, wherein the plunger assembly comprises a multi-layered structure comprising at least an interposer substrate sandwiched by a top socket and a nest (see claim 1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GIOVANNI ASTACIO-OQUENDO whose telephone number is (571)270-5724. The examiner can normally be reached Monday - Friday, 8:00am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GIOVANNI ASTACIO-OQUENDO/ Primary Examiner, Art Unit 2858 4/18/2026
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