DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/18/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-4, 6, 8 and 10 of U.S. Patent No. 12,148,837. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 2, Pat '837 discloses, in claims 1, 4, and 8, a device comprising:
a first dielectric layer; a channel region over the first dielectric layer; a source/drain region adjacent the channel region; a second dielectric layer over the source/drain region; a conductive via extending through the second dielectric layer, the source/drain region, and the first dielectric layer; and a metal-semiconductor alloy region disposed between the conductive via and the source/drain region ("a first dielectric layer; a channel region over the first dielectric layer; a gate structure over the channel region; a source/drain region adjacent the gate structure; a second dielectric layer over the source/drain region; and a conductive via extending through the second dielectric layer and the first dielectric layer, a top surface of the conductive via being coplanar with a top surface of the gate structure", “the conductive via extends through the source/drain region”, and “a metal-semiconductor alloy region disposed between the conductive via and the sidewall of the source/drain region”, in claims 1, 4, and 8 of Pat '525, are interpreted as the same limitation). as described above.
Regarding claim 3, Pat '837 discloses the device of claim 2 as described above.
Pat '837 does not explicitly disclose a power rail connected to the conductive via, wherein the power rail is disposed on a side of the first dielectric layer opposite to the channel region.
Pat '837 teaches, in claim 10, a power rail connected to the conductive via, wherein the power rail is disposed on a side of the first dielectric layer opposite to the channel region ("the device layer comprising a transistor; and a conductive via extending through the device layer, the conductive via connecting the power rail to the conductive line", in claim 10 of Pat '837, is interpreted as the same limitation), for the purpose of providing conductive vias connecting the conductive features of the back-side interconnect structure to the conductive features of the front-side interconnect structure through the device layer thereby improving the performance of the resulting semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claims 1, 4, and 8 of Pat '837to have the power rail connected to the conductive via, wherein the power rail is disposed on a side of the first dielectric layer opposite to the channel region, as taught by claim 10 of Pat '837, for the purpose of providing conductive vias connecting the conductive features of the back-side interconnect structure to the conductive features of the front-side interconnect structure through the device layer thereby improving the performance of the resulting semiconductor devices.
Regarding claim 4, Pat '837 discloses the device of claim 2 as described above.
Pat '837 further discloses, in claim 3, a bottom surface of the conductive via is coplanar with a bottom surface of the first dielectric layer, and a top surface of the conductive via is coplanar with a top surface of the second dielectric layer (all limitations are the same with the limitations recited in claim 3 of Pat '837).
Regarding claim 5, Pat '837 discloses the device of claim 2 as described above.
Pat '837 further discloses, in claim 6, a first source/drain contact extending through the first dielectric layer and into a lower portion of the source/drain region; and a second source/drain contact extending through the second dielectric layer and into an upper portion of the source/drain region, the second source/drain contact physically and electrically coupled to the first source/drain contact (all limitations are the same with the limitations recited in claim 6 of Pat '837).
Claims 10-12 and 14-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-11 and 14 of U.S. Patent No. 12,148,837 in view of Rubin (US 2020/0135646).
Regarding claim 10, Pat '837 discloses, in claims 10 and 14, a device comprising:
a first interconnect structure comprising a conductive line; a second interconnect structure comprising a power rail; a device layer between the first interconnect structure and the second interconnect structure; and a conductive via extending through the device layer, the conductive via connecting the power rail to the conductive line (all limitations are the same with the limitations recited in claim 10 of Pat '837); a width of the power rail being greater than a width of the conductive line ("a width of the power rail is greater than a width of the conductive line ", in claim 14 of Pat '837, is interpreted as the same limitation).
Pat '837 does not explicitly disclose a first interconnect structure comprising a conductive line in a first level of the first interconnect structure.
Rubin teaches, in at least figure 1 and related text, the device comprising a first interconnect structure (BEOL, [41]) comprising a conductive line (M0, [41]) in a first level of the first interconnect structure, for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5]) thereby improving density of integration.
Pat '837 and Rubin are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '837 with the specified features of Rubin because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '837 to have the first interconnect structure comprising a conductive line in a first level of the first interconnect structure, as taught by Rubin, for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5], Rubin) thereby improving density of integration.
Regarding claim 11, Pat '837 in view of Rubin discloses the device of claim 10 as described above.
Pat '837 further discloses, in claims 10 and 11, the device layer comprises a source/drain region, and the conductive via extends through the source/drain region ("the device layer comprising a transistor" and “the transistor comprises a source/drain region, and the conductive via extends through the source/drain region”, in claims 10 and 11 of Pat '837, are interpreted as the same limitation)
Regarding claim 12, Pat '837 in view of Rubin discloses the device of claim 10 as described above.
Rubin further teaches, in at least figure 1 and related text, the device layer (T1/T2, [37]) comprises a source/drain region ([38]) and a dielectric feature (118/128, [37], [40]) adjacent to the source/drain region ([38]), and the conductive via (134, [45]) extends through the dielectric feature (118/128, [37], [40]), for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5]) thereby improving density of integration.
Regarding claim 14, Pat '837 in view of Rubin discloses the device of claim 10 as described above.
Rubin further teaches, in at least figure 1 and related text, the conductive via (134, [45]) comprises a plurality of stacked contacts (figure), for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5]) thereby improving density of integration.
Regarding claim 15, Pat '837 in view of Rubin discloses the device of claim 10 as described above.
Rubin further teaches, in at least figure 1 and related text, the width of the power rail (102, [45]) is at least twice the width of the conductive line (134, [45]) (figure), for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5]) thereby improving density of integration.
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10 and 14 of U.S. Patent No. 12,148,837 in view of Rubin (US 2020/0135646), and further in view of Jakushokas (US 2015/0294970).
Regarding claim 13, Pat '837 in view of Rubin discloses the device of claim 10 as described above.
Pat '837 in view of Rubin does not explicitly disclose the second interconnect structure further comprises a passive device connected to the power rail.
Jakushokas teaches, in at least figure 3 and related text, the device comprising the second interconnect structure (BEOL, [32]) further comprises a passive device (115/130, [33]) connected to the power rail (150/160, [33]), for the purpose of providing a decoupling capacitor to decouple noise from the power rail and a damping resistor to dampen ringing on the power rail ([33]).
Pat '837, Rubin, and Jakushokas are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '837 in view of Rubin with the specified features of Jakushokas because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '837 in view of Rubin to have the second interconnect structure further comprising a passive device connected to the power rail, as taught by Jakushokas, for the purpose of providing a decoupling capacitor to decouple noise from the power rail and a damping resistor to dampen ringing on the power rail ([33], Jakushokas).
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 of U.S. Patent No. 12,148,837 in view of Jakushokas (US 2015/0294970).
Regarding claim 16, Pat '837 discloses, in claim 15, a device comprising:
a first interconnect structure comprising metallization patterns; a second interconnect structure comprising a power; a device layer between the first interconnect structure and the second interconnect structure, the device layer comprising active devices, the metallization patterns interconnecting the active devices to form a functional circuit; and a conductive via extending through the device layer, the conductive via connecting the power to the functional circuit ("a first interconnect structure comprising metallization patterns; a second interconnect structure comprising power rails; a device layer between the first interconnect structure and the second interconnect structure, the device layer comprising active devices, the metallization patterns interconnecting the active devices to form functional circuits, the power rails providing a reference/supply voltage to the functional circuits; and a conductive via extending through the device layer, the conductive via connecting one of the power rails to one of the metallization patterns", in claim 15 of Pat '837, is interpreted as the same limitation).
Pat '837 does not explicitly disclose a second interconnect structure comprising a power circuit.
Jakushokas teaches, in at least figure 3 and related text, the device comprising a second interconnect structure (BEOL, [32]) comprising a power circuit (150/160/115/130, [33]), for the purpose of providing a decoupling capacitor to decouple noise from the power rail and a damping resistor to dampen ringing on the power rail ([33]).
Pat '837 and Jakushokas are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '837 with the specified features of Jakushokas because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '837 in view of Rubin to have the second interconnect structure comprising a power circuit, as taught by Jakushokas, for the purpose of providing a decoupling capacitor to decouple noise from the power rail and a damping resistor to dampen ringing on the power rail ([33], Jakushokas).
Claims 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 of U.S. Patent No. 12,148,837 in view of Jakushokas (US 2015/0294970), and further in view of Rubin (US 2020/0135646).
Regarding claim 17, Pat '837 in view of Jakushokas discloses the device of claim 16 as described above.
Jakushokas further teaches, in at least figure 3 and related text, the power circuit (150/160/115/130, [33]) comprises a passive device (115/130, [33]) and a power rail (150/160, [33]), for the purpose of providing a decoupling capacitor to decouple noise from the power rail and a damping resistor to dampen ringing on the power rail ([33]).
Pat '837 in view of Jakushokas does not explicitly disclose the conductive via physically contacting the power rail.
Rubin teaches, in at least figure 1 and related text, the device comprising the conductive via (134, [45]) physically contacting the power rail (102, [45]) (figure), for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5]) thereby improving density of integration.
Pat '837, Jakushokas, and Rubin are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '837 in view of Jakushokas with the specified features of Rubin because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '837 in view of Jakushokas to have the conductive via physically contacting the power rail, as taught by Rubin, for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5], Rubin) thereby improving density of integration.
Regarding claim 18, Pat '837 in view of Jakushokas and Rubin discloses the device of claim 17 as described above.
Rubin further teaches, in at least figure 1 and related text, a width of the power rail (102, [45]) is at least twice a width of a first level conductive line (M0, [41]) of the metallization patterns (figure), for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5]) thereby improving density of integration.
Regarding claim 19, Pat '837 in view of Jakushokas discloses the device of claim 16 as described above.
Pat '837 in view of Jakushokas does not explicitly disclose the conductive via extends through a semiconductive feature of the device layer.
Rubin teaches, in at least figure 1 and related text, the device comprising the conductive via (134, [45]) extends through a semiconductive feature (110/120, [36], [39]) of the device layer (T1/T2, [36]) (figure), for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5]) thereby improving density of integration.
Pat '837, Jakushokas, and Rubin are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '837 in view of Jakushokas with the specified features of Rubin because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '837 in view of Jakushokas to have the conductive via extending through a semiconductive feature of the device layer, as taught by Rubin, for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5], Rubin) thereby improving density of integration.
Regarding claim 20, Pat '837 in view of Jakushokas discloses the device of claim 16 as described above.
Pat '837 in view of Jakushokas does not explicitly disclose the conductive via extends through a dielectric feature of the device layer.
Rubin teaches, in at least figure 1 and related text, the device comprising the conductive via (134, [45]) extends through a dielectric feature (118/128, [37], [40]) of the device layer (T1/T2, [36]) (figure), for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5]) thereby improving density of integration.
Pat '837, Jakushokas, and Rubin are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '837 in view of Jakushokas with the specified features of Rubin because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '837 in view of Jakushokas to have the conductive via extending through a dielectric feature of the device layer, as taught by Rubin, for the purpose of providing monolithic 3D semiconductor IC devices comprising power distribution networks which are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers ([5], Rubin) thereby improving density of integration.
Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 of U.S. Patent No. 12,148,837 in view of Jakushokas (US 2015/0294970), and further in view of Sinha (US 2017/0365600).
Regarding claim 21, Pat '837 in view of Jakushokas discloses the device of claim 16 as described above.
Pat '837 in view of Jakushokas does not explicitly disclose an external connector on the second interconnect structure, the external connector connected to the power circuit.
Sinha teaches, in at least figure 2 and related text, the device comprising an external connector (275, [39]) on the second interconnect structure (220, [35]), the external connector (275, [39]) connected to the power circuit (210, [35]) (figure), for the purpose of providing monolithic 3D IC having a plurality of tiers disposed on top of one another on a substrate layer in a vertical direction ([21]) thereby improving density of integration.
Pat '837, Jakushokas, and Sinha are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '837 in view of Jakushokas with the specified features of Sinha because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '837 in view of Jakushokas to have the external connector on the second interconnect structure, the external connector connected to the power circuit, as taught by Sinha, for the purpose of providing monolithic 3D IC having a plurality of tiers disposed on top of one another on a substrate layer in a vertical direction ([21], Sinha) thereby improving density of integration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10, 12 and 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rubin (US 2020/0135646).
Regarding claim 10, Rubin discloses, in at least figure 1 and related text, a device comprising:
a first interconnect structure (BEOL, [41]) comprising a conductive line (M0, [41]) in a first level of the first interconnect structure (BEOL, [41]);
a second interconnect structure (BSL, [36]) comprising a power rail (102, [36]), a width of the power rail (102, [36]) being greater than a width of the conductive line (M0, [41]);
a device layer (T1/T2, [36]) between the first interconnect structure (BEOL, [41]) and the second interconnect structure (BSL, [36]); and
a conductive via (134, [45]) extending through the device layer (T1/T2, [36]), the conductive via (134, [45]) connecting the power rail (102, [36]) to the conductive line (M0, [41]).
Regarding claim 12, Rubin discloses the device of claim 10 as described above.
Rubin further discloses, in at least figure 1 and related text, the device layer (T1/T2, [37]) comprises a source/drain region ([38]) and a dielectric feature (118/128, [37], [40]) adjacent to the source/drain region ([38]), and the conductive via (134, [45]) extends through the dielectric feature (118/128, [37], [40]).
Regarding claim 14, Rubin discloses the device of claim 10 as described above.
Rubin further discloses, in at least figure 1 and related text, the conductive via (134, [45]) comprises a plurality of stacked contacts (figure).
Regarding claim 15, Rubin discloses the device of claim 10 as described above.
Rubin further discloses, in at least figure 1 and related text, the width of the power rail (102, [45]) is at least twice the width of the conductive line (134, [45]) (figure).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rubin (US 2020/0135646) in view of Jakushokas (US 2015/0294970).
Regarding claim 13, Rubin discloses the device of claim 10 as described above.
Rubin does not explicitly disclose the second interconnect structure further comprises a passive device connected to the power rail.
Jakushokas teaches, in at least figure 3 and related text, the device comprising the second interconnect structure (BEOL, [32]) further comprises a passive device (115/130, [33]) connected to the power rail (150/160, [33]), for the purpose of providing a decoupling capacitor to decouple noise from the power rail and a damping resistor to dampen ringing on the power rail ([33]).
Rubin and Jakushokas are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Rubin with the specified features of Jakushokas because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Rubin to have the second interconnect structure further comprising a passive device connected to the power rail, as taught by Jakushokas, for the purpose of providing a decoupling capacitor to decouple noise from the power rail and a damping resistor to dampen ringing on the power rail ([33], Jakushokas).
Regarding claim 16, Rubin discloses, in at least figure 1 and related text, a device comprising:
a first interconnect structure (BEOL, [41]) comprising metallization patterns (M0-M3/V0-V2, [41]);
a second interconnect structure (BSL, [36]) comprising a power (102, [36]);
a device layer (T1/T2, [36]) between the first interconnect structure (BEOL, [41]) and the second interconnect structure (BSL, [36]), the device layer (T1/T2, [36]) comprising active devices (FinFET, [36]), the metallization patterns (M0-M3/V0-V2, [41]) interconnecting the active devices (FinFET, [36]) to form a functional circuit ([42]); and
a conductive via (134, [45]) extending through the device layer (T1/T2, [36]), the conductive via (134, [45]) connecting the power (102, [36]) to the functional circuit.
Rubin does not explicitly disclose a second interconnect structure comprising a power circuit.
Jakushokas teaches, in at least figure 3 and related text, the device comprising a second interconnect structure (BEOL, [32]) comprising a power circuit (150/160/115/130, [33]), for the purpose of providing a decoupling capacitor to decouple noise from the power rail and a damping resistor to dampen ringing on the power rail ([33]).
Rubin and Jakushokas are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Rubin with the specified features of Jakushokas because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Rubin to have the second interconnect structure comprising a power circuit, as taught by Jakushokas, for the purpose of providing a decoupling capacitor to decouple noise from the power rail and a damping resistor to dampen ringing on the power rail ([33], Jakushokas).
Regarding claim 17, Rubin in view of Jakushokas discloses the device of claim 16 as described above.
Rubin further discloses, in at least figure 1 and related text, the conductive via (134, [45]) physically contacting the power rail (102, [45]) (figure).
Jakushokas further teaches, in at least figure 3 and related text, the power circuit (150/160/115/130, [33]) comprises a passive device (115/130, [33]) and a power rail (150/160, [33]), for the purpose of providing a decoupling capacitor to decouple noise from the power rail and a damping resistor to dampen ringing on the power rail ([33]).
Regarding claim 18, Rubin in view of Jakushokas discloses the device of claim 17 as described above.
Rubin further discloses, in at least figure 1 and related text, a width of the power rail (102, [45]) is at least twice a width of a first level conductive line (M0, [41]) of the metallization patterns (figure).
Regarding claim 19, Rubin in view of Jakushokas discloses the device of claim 16 as described above.
Rubin further discloses, in at least figure 1 and related text, the device comprising the conductive via (134, [45]) extends through a semiconductive feature (110/120, [36], [39]) of the device layer (T1/T2, [36]) (figure).
Regarding claim 20, Rubin in view of Jakushokas discloses the device of claim 16 as described above.
Rubin further discloses, in at least figure 1 and related text, the conductive via (134, [45]) extends through a dielectric feature (118/128, [37], [40]) of the device layer (T1/T2, [36]) (figure).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rubin (US 2020/0135646) in view of Jakushokas (US 2015/0294970), and further in view of Sinha (US 2017/0365600).
Regarding claim 21, Rubin in view of Jakushokas discloses the device of claim 16 as described above.
Rubin in view of Jakushokas does not explicitly disclose an external connector on the second interconnect structure, the external connector connected to the power circuit.
Sinha teaches, in at least figure 2 and related text, the device comprising an external connector (275, [39]) on the second interconnect structure (220, [35]), the external connector (275, [39]) connected to the power circuit (210, [35]) (figure), for the purpose of providing monolithic 3D IC having a plurality of tiers disposed on top of one another on a substrate layer in a vertical direction ([21]) thereby improving density of integration.
Rubin, Jakushokas, and Sinha are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Rubin in view of Jakushokas with the specified features of Sinha because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Rubin in view of Jakushokas to have the external connector on the second interconnect structure, the external connector connected to the power circuit, as taught by Sinha, for the purpose of providing monolithic 3D IC having a plurality of tiers disposed on top of one another on a substrate layer in a vertical direction ([21], Sinha) thereby improving density of integration.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 2, 5, and 6 that recite "a first portion between the first source/drain contact and the lower portion of the source/drain region; a second portion between the second source/drain contact and the upper portion of the source/drain region, wherein the first portion and the second portion have a distinguishable interface" in combination with other elements of the base claims 2, 5, and 6.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 2, 5, and 7 that recite "a first portion between the first source/drain contact and the lower portion of the source/drain region; a second portion between the second source/drain contact and the upper portion of the source/drain region, wherein the first portion and the second portion have no distinguishable interface" in combination with other elements of the base claims 2, 5, and 7.
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 2, 5, and 8 that recite "the first source/drain contact extends into the lower portion of the source/drain region by a same distance as the second source/drain contact extends into the upper portion of the source/drain region" in combination with other elements of the base claims 2, 5, and 8.
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 2, 5, and 9 that recite "the first source/drain contact has a first height, the second source/drain contact has a second height, and the first height is less than the second height" in combination with other elements of the base claims 2, 5, and 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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