DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 11 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching et al. (US 2018/0350969 A1).
Regarding claim 11, Ching teaches a semiconductor structure (100 in Fig. 1 of Ching), comprising:
a first fin (108A/B);
an isolation structure (106) adjacent the fin;
a first oxide layer (112) adjacent the first fin and the isolation structure; and
a second oxide layer (114) adjacent the first oxide layer, the first oxide layer and the second oxide layer defining a composite oxide layer (combination of 112 and 114), wherein a horizontal portion (112A and horizontal portion of 114 on top of the fin) of the composite oxide layer is thicker than a vertical portion (112B and vertical portion of 114 on sidewalls of fin) of the composite oxide layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2017/0033013 A1) in view of Ching et al. (US 2018/0350969 A1).
Regarding claim 1, Kim teaches a semiconductor structure (integrated circuit device in Figs. 7A-7L of Kim which is an embodiment of Figs. 3A-3C), comprising:
a first fin (FA1 in Fig. 7L);
an isolation structure (112 in Fig. 7L) adjacent the first fin;
a dielectric layer (174 in Fig. 3C) adjacent the isolation structure;
a first oxide layer (122A) adjacent the first fin, the isolation structure, and the dielectric layer; and
a second oxide layer (interface layer 124A and high-k dielectric layer 126A) adjacent the first oxide layer, the first oxide layer and the second oxide layer defining a composite oxide layer (120A),
But Kim does not teach that wherein a horizontal portion of the composite oxide layer is thicker than a vertical portion of the composite oxide layer.
Ching teaches a finFET device (100 in Fig. 1 of Ching) comprising: a fin structure (108) on a substrate (102); an isolation structure (106) adjacent the fin structure; an oxide layer (112) disposed over the fin structure and the isolation structure wherein a horizontal portion (112A) of the oxide layer is thicker than a vertical portion (112B) of the oxide layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the first oxide layer (122A of Kim) as according to Ching’s method in order to avoid overhang structure in the 7nm technology node and beyond (see [0011] of Ching).
Regarding claim 2, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 1, but does not teach explicitly wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer.
Kim teaches that the thickness of the oxide layer 122A has thickness in the range of 1nm to 5 nm (see [0159] of Kim). Some of this thickness actually belongs to the second oxide layer (as defined in claim 14 above). Kim also discloses that the interface layer (124) has thickness in the range of 0.5 nm to 2 nm (see [0165] of Kim), and the high-k dielectric layer (126A) has thickness in the range of 1 nm to 4 nm (see [0168] of Kim) so the second oxide layer has thickness in the range of 1.5nm to 6nm.
Since it has been held that in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the thickness of the second oxide layer is greater than the thickness of the first oxide layer. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Regarding claim 3, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the first fin is an input/output fin ([0099] of Kim) that operates at a first voltage (operating voltage of TR11 in region I of Kim).
Regarding claim 4, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 3, and further comprising a second fin (FA2 in Figs. 6A-6C of Kim) that is a core fin that operates at a second voltage (as described in [0099] of Kim).
Regarding claim 5, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 4, and further comprising a gate (140A in Fig. 6A-6C of Kim) formed adjacent the second oxide layer and adjacent the second fin.
Regarding claim 6, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the second voltage is less than the first voltage (as described in [0099] of Kim).
Regarding claim 7, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 1, and further comprising a gate (140A in Fig. 6A-6C of Kim) formed adjacent the second oxide layer.
Regarding claim 8, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the isolation structure comprises a shallow trench isolation (STI) structure (as shown in Fig. 6B of Kim).
Regarding claim 9, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the dielectric layer comprises an inter-layer dielectric (ILD) structure (as shown in Fig. 6C of Kim).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ching, and further in view of Liao et al. (US 2018/0033866 A1).
Regarding claim 10, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 1, but does not teach wherein the dielectric layer comprises a contact etch stop layer (CESL) formed on a side surface of the dielectric layer.
Liao teaches a semiconductor device (2 in Fig. 16 of Liao) comprising: a contact etch stop layer (CESL) (40) and an ILD layer (42) on the gate and fin structures; S/D contact plugs (70) formed through the ILD and CESL layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the CESL before the dielectric layer as disclosed by Liao in order to further protect the device when forming the S/D contact plugs.
Claims 11-13, 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ching.
Regarding claim 11, Kim teaches a semiconductor structure (integrated circuit device in Figs. 7A-7L of Kim which is an alternative embodiment of Figs. 3A-3C), comprising:
a first fin (FA1 in Fig. 7L);
an isolation structure (112) adjacent the fin;
a first oxide layer (122A) adjacent the first fin and the isolation structure; and
a second oxide layer (interface layer 124A and high-k dielectric layer 126A) adjacent the first oxide layer, the first oxide layer and the second oxide layer defining a composite oxide layer (120A).
But Kim does not teach that wherein a horizontal portion of the composite oxide layer is thicker than a vertical portion of the composite oxide layer.
Ching teaches a finFET device (100 in Fig. 1 of Ching) comprising: a fin structure (108) on a substrate (102); an isolation structure (106) adjacent the fin structure; an oxide layer (112) disposed over the fin structure and the isolation structure wherein a horizontal portion (112A) of the oxide layer is thicker than a vertical portion (112B) of the oxide layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the first oxide layer (122A of Kim) as according to Ching’s method in order to avoid overhang structure in the 7nm technology node and beyond (see [0011] of Ching).
Regarding claim 12, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 11, and also teaches the semiconductor structure further comprising a dielectric layer (ILD 174 in Fig. 7C of Kim) adjacent the composite oxide layer.
Regarding claim 13, Kim in view of Ching in view of Liao teaches all limitations of the semiconductor structure of claim 12, and also teaches wherein the dielectric layer comprises an inter-layer dielectric (ILD) structure (174 of Kim).
Regarding claim 15, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 11, but does not explicitly teach wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer.
Kim teaches that the thickness of the oxide layer 122A has thickness in the range of 1nm to 5 nm (see [0159] of Kim). Some of this thickness actually belongs to the second oxide layer (as defined in claim 14 above). Kim also discloses that the interface layer (124) has thickness in the range of 0.5 nm to 2 nm (see [0165] of Kim), and the high-k dielectric layer (126A) has thickness in the range of 1 nm to 4 nm (see [0168] of Kim) so the second oxide layer has thickness in the range of 1.5nm to 6nm.
Since it has been held that in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the thickness of the second oxide layer is greater than the thickness of the first oxide layer. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Regarding claim 16, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 11, and also teaches wherein the first fin is an input/output fin that operates at a first voltage (as disclosed in ([0099] of Kim).
Regarding claim 17, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 16, and further comprising a second fin (FA2 in Fig. 7L of Kim) that is a core fin that operates at a second voltage, wherein the second voltage is less than the first voltage (as disclosed in ([0099] of Kim).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ching, and further in view of Liao.
Regarding claim 14, Kim in view of Ching in view of Liao teaches all limitations of the semiconductor structure of claim 12, but does not teach wherein the dielectric layer comprises a contact etch stop layer (CESL) formed on a side surface of the dielectric layer.
Liao teaches a semiconductor device (2 in Fig. 16 of Liao) comprising: a contact etch stop layer (CESL) (40) and an ILD layer (42) on the gate and fin structures; S/D contact plugs (70) formed through the ILD and CESL layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the CESL before the dielectric layer as disclosed by Liao in order to further protect the device when forming the S/D contact plugs.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ching.
Regarding claim 18, Kim teaches a semiconductor structure (integrated circuit device in Figs. 7A-7L of Kim which is an embodiment of Figs. 3A-3C), comprising:
a first fin (FA1 in Fig. 7L);
a dielectric layer (174 in Fig. 7L) adjacent the first fin the isolation structure;
a first oxide layer (122A) adjacent the first fin and the dielectric layer; and
a second oxide layer (interface layer 124A and high-k dielectric layer 126A) adjacent the first oxide layer, the first oxide layer and the second oxide layer defining a composite oxide layer (120A).
But Kim does not teach that wherein a horizontal portion of the composite oxide layer is thicker than a vertical portion of the composite oxide layer.
Ching teaches a finFET device (100 in Fig. 1 of Ching) comprising: a fin structure (108) on a substrate (102); an isolation structure (106) adjacent the fin structure; an oxide layer (112) disposed over the fin structure and the isolation structure wherein a horizontal portion (112A) of the oxide layer is thicker than a vertical portion (112B) of the oxide layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the first oxide layer (122A of Kim) as according to Ching’s method in order to avoid overhang structure in the 7nm technology node and beyond (see [0011] of Ching).
Regarding claim 19, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 18, and further comprising an isolation structure (112 in Fig. 7L of Kim) adjacent the first fin and the dielectric layer.
Regarding claim 20, Kim in view of Ching teaches all limitations of the semiconductor structure of claim 18, but does not explicitly teach wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer.
Kim teaches that the thickness of the first oxide layer (122A of Kim) has thickness in the range of 1nm to 5 nm (see [0159] of Kim). Kim also discloses that the interface layer (124) has thickness in the range of 0.5 nm to 2 nm (see [0165] of Kim), and the high-k dielectric layer (126A) has thickness in the range of 1 nm to 4 nm (see [0168] of Kim) so the second oxide layer has thickness in the range of 1.5nm to 6nm.
Since it has been held that in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the thickness of the second oxide layer is greater than the thickness of the first oxide layer. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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