DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/13/2024; 8/21/2025; and 3/10/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Applicant’s 9/4/2024 Preliminary Amendment to: 1. Amend the instant Specification. 2. Amend the Claims is acknowledged.
Claims Status
Claims 1-20 are currently pending and being examined.
Claim Objections
Claim 16 is objected to because of the following informalities: The grammatical error “wherein width of” in line 1. For examination purposes, “wherein width of” in line 1 will be interpreted to read as “wherein a width of”. Appropriate correction is required.
Allowable Subject Matter
Claims 6-7; 9, 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
A. Re claim 6, the prior art cannot be used to satisfy the limitations of: wherein the forming a reduced gate dielectric includes: forming a mask layer on the gate dielectric, the mask layer covering the gate spacer; forming a reduced mask layer by removing a portion of the mask layer by etching the mask layer using the dielectric protective layer as a first mask; and etching the gate dielectric using the reduced mask layer as a second mask, in combination with the limitations of claim 1.
B. Re claim 7, the prior art cannot be used to satisfy the limitations of: wherein the forming the reduced mask layer includes forming the reduced mask layer having a tapered profile that increases in width with proximity to the substrate, in combination with the limitations of claims 1 and 6.
C. Re claim 9, the prior art cannot be used to satisfy the limitations of: wherein the forming the reduced gate dielectric includes: forming a mask layer on the gate dielectric, the mask layer covering the gate spacer; forming a reduced mask layer by removing a portion of the mask layer by etching the mask layer using the capping layer as a first mask; and etching the gate dielectric using the reduced mask layer as a second mask, in combination with the limitations of claim 8.
D. Re claim 11, the prior art cannot be used to satisfy the limitations of: wherein the forming the dielectric protective layer includes: forming a stack of first semiconductor layers and second semiconductor layers that is associated with the stack of alternating first nanostructures and second nanostructures; forming a third semiconductor layer on the stack of first and second semiconductor layers; forming a third nanostructure by forming a source or drain opening that extends through the stack of first and second semiconductor layers and the third semiconductor layer; forming an opening by removing the third nanostructure; and forming the dielectric protective layer in the opening, in combination with the limitations of claim 8.
E. Re claim 12, the prior art cannot be used to satisfy the limitations of: wherein the forming the dielectric protective layer in the opening is conducted during the forming inner spacers between the first nanostructures, in combination with the limitations of claims 8 and 11.
F. Re claim 13, the prior art cannot be used to satisfy the limitations of: wherein the forming the third semiconductor layer includes forming the third semiconductor layer having a germanium concentration that exceeds those of the first and second semiconductor layers, in combination with the limitations of claims 8 and 11.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bao (US 2025/0203934 A1).
Re claim 1 Bao discloses in FIGS. 1A-10D a method, comprising:
forming a stack ([0035]) including alternating first semiconductor layers (230; [0035]) and second semiconductor layers (220; [0035]) on a substrate (200; [0035]);
forming a sacrificial gate (270; [0035]) structure on the stack;
forming a gate spacer (280; [0035]) adjacent the sacrificial gate structure (270);
releasing ([0038]) the first semiconductor layers (230) by removing the second semiconductor layers (220);
forming a gate dielectric (as formed 410; [0046]) on the first semiconductor layers (230) and a side surface (left/right inner walls) of the gate spacer (280);
forming a reduced (recessed; [0005] and [0047]) gate dielectric (410) by removing a portion (upper part) of the gate dielectric (as formed 410) from the side surface (left/right inner walls) of the gate spacer (280), the portion (upper part) being laterally adjacent (at left/right source/drain 260) to the first semiconductor layers (230); and
forming a gate metal layer (900/910; [0046]-[0047]) on the reduced gate dielectric (410) and exposed portions (upper part of left/right inner walls) of the gate spacer (280).
Re claims 2-4, Bao discloses the method of claim 1, further comprising: prior to the forming (FIG. 9A) a sacrificial gate structure (270), forming (FIG. 2A) a dielectric protective layer (240; [0035]) over the stack; wherein the forming (FIG. 2A) the dielectric protective layer (240) over the stack includes forming the dielectric protective layer (240) that has a width (maximum lateral extension) that exceeds (extends beyond) those (maximum overlap of extension of 220 or orthogonal projection of 270 on 230) of the first semiconductor layers (230); and wherein the forming the dielectric protective layer (240) over the stack includes forming (FIG. 2A) the dielectric protective layer (240) that has width that is substantially same (equal) as that of at least one (all) of the first semiconductor layers (230).
Re claim 5, Bao disclose the method of claim 2, wherein the forming the gate dielectric (as formed 410) includes forming (FIG. 4A) the gate dielectric (as formed 410) on (left/right inner walls of) the dielectric protective layer.
Claims 15-16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang et al (US 2021/0057535 A1, hereafter Chiang).
Re claim 15, Chiang discloses in FIG. 1O a device (100a), comprising:
a stack of nanostructures (106’; [0061]);
a first layer (108’’; [0063]) over (on) and offset from (laterally beyond) the stack of nanostructures (106’);
an inner spacer (left/right 134; [0049]) between the first layer (108’) and the stack of nanostructures (106’); and
a gate structure (156; [0066]) wrapping around the stack of nanostructures (106’), the gate structure (156) including:
a gate dielectric (148; [0066]) on the nanostructures (106’) and between the inner spacer (left/right 134) and the nanostructures (each 106’) of the stack of nanostructures (106’); and
a gate metal (150/152/154; [0066] and [0069]-[0071]) on the gate dielectric (148).
Re claim 16, Chiang disclose the device of claim 15, wherein a width (lateral extension) of the first layer (108’’) exceeds (extends beyond) widths (lateral overlap of each 156) of the nanostructures (each 106’) of the stack of nanostructures (106’).
Re claim 18, Chiang discloses the device of claim 15, wherein the gate dielectric (148) is adjacent to (on) more than one side (upper/lower planes) of the first layer (108’’).
Re claim 19, Chiang he device of claim 18, wherein a first portion (in recessed trench portion 142; [0063]) of the gate dielectric (148) on a top surface (upper plane) of the first layer (108’’) has thickness (vertical extension) that is less (shorter in FIGS. 1O and 2C-1) than that of a second portion (on uppermost left/right 134) of the gate dielectric (148) on a bottom surface (lower plane) of the first layer (108’’).
Re claim 20, Chiang disclose the device of claim 15, wherein a portion of the gate dielectric (148) that is below the first layer (108’) has substantially uniform width (same lateral extension) between the first layer (108’) and a bottommost (lowest) nanostructure (106’) of the stack of nanostructures (106’).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8, 10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bao in view of Xie et al (US 2022/0165575 A1, hereafter Xie).
Re claim 8, Bao discloses in FIGS. 1A-10D a method, comprising:
forming a dielectric protective layer (240; [0035]) over a stack of alternating first nanostructures and second nanostructures (see claim 1);
forming a gate spacer (see claim 1) adjacent the first nanostructures (see claim 1);
forming inner spacers (250; [0036]) between the first nanostructures (see claim 1);
releasing the first nanostructures by removing the second nanostructures (see claim 1);
forming a gate dielectric on the first nanostructures (see claim 1), the dielectric protective layer (240) and the gate spacer (see claim 1);
forming a reduced gate dielectric by removing a first portion (left side on left 280) of the gate dielectric from a side surface of the gate spacer (see claim 1), the portion having a width (lateral extension) substantially equal to that (the same lateral extension as region of 400) of the dielectric protective layer (240); and
forming a gate metal layer on the reduced gate dielectric and exposed portions of the gate spacer (see claim 1).
Bao fails to disclose forming a capping layer on the dielectric protective layer (240), the capping layer having a width exceeding that of the dielectric protective layer (240).
However,
Xie discloses in FIGS. 8-9 a method comprising: depositing a high-k dielectric layer ([0075] and [0083]) and a threshold voltage shifting layer ([0075] and [0083]) laminate on a substrate ([0290]), forming a capping layer (TiN; [0289]) on the high-k dielectric layer, and etching the laminate ([0290]-[0297]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Bao, by using the capping layer of Xie, forming the capping layer (see inserted figure below) on the dielectric protective layer (240), the capping layer having a width exceeding that of the dielectric protective layer (240), to effect the reducing of the gate dielectric, which provides a manufacturable way to integrate on a single substrate both logic nanosheet transistors and input/output (“I/O”) nanosheet transistors, and a reduced gate resistance of a transistor (Bao; [0030]).
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For the record, the inserted figure (annotated FIG. 4A of Bao) depicts the capping layer of Xie applied on the dielectric protective layer (240). The capping layer has a wider width than the dielectric protective layer (240) and depicted to be consistent with the process of Xie (FIG. 9) and the process of Bao (FIG. 9A).
Re claim 10, Bao and Xie disclose the method of claim 8, wherein the forming the capping layer (of Xie) includes forming a transition metal nitride layer (Xie: TiN; [0289]) on the dielectric protective layer (240 of Bao), as part of the reduced gate resistance devices discussed for claim 8.
Re claim 14, Bao discloses the method of claim 8, wherein the forming the reduced gate dielectric (410) includes removing a second portion (right side on right 280) of the gate dielectric (as formed 410) from an upper surface (upper portion of the right sidewall) of the dielectric protective layer (240).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of HICKEY et al (US 2021/0408285 A1, hereafter Hickey).
Re claim 17, Chiang discloses the device of claim 15.
But, fails to discloses wherein the gate dielectric (148) on the inner spacer (left/right 134) has a tapered profile below the first layer (108’).
However,
Hickey discloses in FIG. 2A a device comprising: wherein the gate dielectric (of lowermost portion of gate stack 208; [0046]) on the inner spacer (lowermost left/right 210A; [0046]) has a tapered profile below the first layer (mislabeled dielectric cap 214 as in 314; [0046] and [0062]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Chaing, by using the tapered profile of Hickey, wherein the gate dielectric (148) on the inner spacer (left/right 134) has a tapered profile below the first layer (108’), to facilitate non-planar source/drain structures which uniaxially compressively strain the vertical arrangement of nanostructures (Hickey; [0050]), potentially increasing mobility in the channels of the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US-20190131431-A1 discloses GAA structures with reduced gate dielectric layers, and metal gate electrodes on gate spacers.
US-10312350-B1 GAA structures with dielectric protective layers, reduced gate dielectric layers, and metal gate electrodes on gate spacers.
US-20200303502-A1 discloses GAA structures with dielectric protective layers, reduced gate dielectric layers, and metal gate electrodes on gate spacers.
US-20210375683-A1 GAA structures with gate dielectric layers of various thicknesses on gate spacers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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