DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8-16 are allowed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 17 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim[1] et al., US Publication No. 2016/0293717 A1.
Kim[1] anticipates:
1. A semiconductor structure, comprising (see figs. 1-4):
a gate structure (145/147) over a channel region (105);
a gate spacer (142) extending along a sidewall surface of the gate structure;
a p-type doped epitaxial source/drain feature (112/114/116; e.g. SiGe at para. [0060]) coupled to the channel region and having a concave top surface, wherein the p-type doped epitaxial source/drain feature comprises a first epitaxial layer (114) and a second epitaxial layer (116) over the first epitaxial layer, wherein the second epitaxial layer has a melting temperature lower than the first epitaxial layer (e.g. SiGe layer 114 has a lower Ge concentration than layer SiGe layer 116 and this results in layer 114 having a lower melting temperature. See Ge concentration at para. [0065].);
a silicide layer (182) disposed over the concave top surface of the p-type doped epitaxial source/drain feature;
a source/drain contact (180a) disposed over the silicide layer and having a convex bottom surface; and
a dielectric spacer (150) providing isolation between the source/drain contact and the gate structure. See Kim[1] at para. [0001] – [0155], figs. 1-23.
3. The semiconductor structure of claim 1, wherein the silicide layer (182) is physically isolated from the first epitaxial layer (114) by the second epitaxial layer (116), fig. 2A.
4. The semiconductor structure of claim 1, wherein the source/drain contact (180a) has an upper portion over a topmost point of the p-type doped epitaxial source/drain feature (112/114/116) and a lower portion under the upper portion, wherein a profile of the lower portion in a cross-sectional view resembles an inverted triangle (e.g. see inverted triangle annotated in fig. 2A below).
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5. The semiconductor structure of claim 4, wherein the inverted triangle is an isosceles triangle, fig. 2A.
17. A semiconductor structure, comprising (see figs. 1-4):
semiconductor fins (105) disposed over a substrate (101);
an isolation feature (107) on the substrate and adjacent to bottom portions of the semiconductor fins;
a p-type source/drain feature (112/114/116) disposed over and merging the semiconductor fins, wherein, in a cross-sectional view cutting through the isolation feature and the p-type source/drain feature, the p-type source/drain feature (112/114/116) has a first sidewall surface (e.g. left sidewall) and a second sidewall surface (e.g. right sidewall) opposing the first sidewall surface, and a curved top surface (e.g. see curved top surface annotated in fig. 4 below) extending from a topmost point of the first sidewall surface to a topmost point of the second sidewall surface;
a silicide layer (182) extending over the top surface of the p-type source/drain feature; and
a source/drain contact (180a) over and electrically coupled to the silicide layer. See Kim[1] at para. [0001] – [0155], figs. 1-23.
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18. The semiconductor structure of claim 17, wherein the top surface of the p-type source/drain feature curves downward (e.g. curves downward at the troughs in fig. 4)
Claim(s) 1-3 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim[2] et al., US Publication No. 2016/0027918 A1..
Kim[2] anticipates:
1. A semiconductor structure, comprising (see fig. 10):
a gate structure (424) over a channel region (ACT/CHR);
a gate spacer (422) extending along a sidewall surface of the gate structure;
a p-type doped epitaxial source/drain feature (380, e.g. silicon germanium, SiGe at para. [0083], para. [0085]) coupled to the channel region and having a concave top surface, wherein the p-type doped epitaxial source/drain feature comprises a first epitaxial layer (384) and a second epitaxial layer (386) over the first epitaxial layer, wherein the second epitaxial layer has a melting temperature lower than the first epitaxial layer (e.g. SiGe layer 384 has a lower Ge concentration than layer SiGe layer 386 and this results in layer 384 having a lower melting temperature. See para. [0084] for Ge concentration);
a silicide layer (430) disposed over the concave top surface of the p-type doped epitaxial source/drain feature;
a source/drain contact (440) disposed over the silicide layer and having a convex bottom surface; and
a dielectric spacer (370) providing isolation between the source/drain contact and the gate structure. See Kim[2] at para. [0001] – [0133], figs. 1-17.
2. The semiconductor structure of claim 1, further comprising:
an etch stop layer (400) extending along a sidewall surface of the second epitaxial layer; and
an interlayer dielectric layer (410) over the etch stop layer, fig. 10D.
3. The semiconductor structure of claim 1, wherein the silicide layer (430) is physically isolated from the first epitaxial layer (384) by the second epitaxial layer (386), fig. 10B.
17. A semiconductor structure, comprising:
semiconductor fins (ACT/CHR) disposed over a substrate (310);
an isolation feature (330) on the substrate and adjacent to bottom portions of the semiconductor fins;
a p-type source/drain feature (380, e.g. silicon germanium, SiGe at para. [0083], para. [0085]) disposed over and merging the semiconductor fins (ACT/CHR), wherein, in a cross-sectional view cutting through the isolation feature and the p-type source/drain feature, the p-type source/drain feature has a first sidewall surface and a second sidewall surface opposing the first sidewall surface, and a curved top surface (e.g. See curved top surface annotated in fig. 10A.) extending from a topmost point of the first sidewall surface to a topmost point of the second sidewall surface;
a silicide layer (430) extending over the top surface of the p-type source/drain feature; and
a source/drain contact (440) over and electrically coupled to the silicide layer. See Kim[2] at para. [0001] – [0133], figs. 1-17.
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18. The semiconductor structure of claim 17, wherein the top surface of the p-type source/drain feature curves downward (e.g. curves downward at the troughs in fig. 10A).
19. The semiconductor structure of claim 17, wherein a distance between the topmost point of the first sidewall surface and a bottommost point of the curved top surface the p-type source/drain feature is substantially equal to a distance between the topmost point of the second sidewall surface and the bottommost point of the curved top surface the p-type source/drain feature (e.g. See fig. 10A annotated to show d1 ~ d2.)
20. The semiconductor structure of claim 17, further comprising:
an etch stop layer (400) extending along the first sidewall surface and the second sidewall surface; and
an interlayer dielectric layer (410) on the etch stop layer,
wherein the etch stop layer (400) and the interlayer dielectric layer (410) are in direct contact with the source/drain contact (380), fig. 10
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim[1], as applied to claim 1 above.
Regarding claim 7:
Kim[1] teaches all the limitations of claim 1 above, and further teaches the second epitaxial layer (116) has a germanium concentration of 50-80% and the first epitaxial layer has a germanium concentration of 20-60%, para. [0065].
Kim[1] is silent “wherein concentration of germanium in the second epitaxial layer is no less than twice of concentration of germanium in the first epitaxial layer”.
However, it would have been obvious to form “wherein concentration of germanium in the second epitaxial layer is no less than twice of concentration of germanium in the first epitaxial layer” because when the concentration germanium in the second epitaxial layer (116) is at the high end of range 80% and the first epitaxial layer has a germanium concentration at the low end of the range 20%, then the claim limitation is met.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim[2], as applied to claim 1 above.
Regarding claim 7:
Kim[2] teaches all the limitations of claim 1 above, and further teaches the second epitaxial layer (386) has a germanium concentration of 50-90 at% and the first epitaxial layer (384) has a germanium concentration of 25-50%, para. [0084].
Kim[2] is silent “wherein concentration of germanium in the second epitaxial layer is no less than twice of concentration of germanium in the first epitaxial layer”.
However, it would have been obvious to form “wherein concentration of germanium in the second epitaxial layer is no less than twice of concentration of germanium in the first epitaxial layer” because when the concentration germanium in the second epitaxial layer (286) is at the high end of range 90% and the first epitaxial layer has a germanium concentration at the low end of the range 25%, then the claim limitation is met.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al., 2017/0053912.
Ching teaches:
17. A semiconductor structure, comprising (see figs. 15-16):
semiconductor fins (302) disposed over a substrate (202);
an isolation feature (402) on the substrate and adjacent to bottom portions of the semiconductor fins;
a p-type source/drain feature (e.g. 1302B, SiGe with dopant at para. [0066]) disposed over and merging the semiconductor fins (302), wherein, in a cross-sectional view cutting through the isolation feature and the p-type source/drain feature, the p-type source/drain feature (1302B) has a first sidewall surface (e.g. left sidewall) and a second sidewall surface (e.g. right sidewall) opposing the first sidewall surface, and a curved top surface (e.g. curved top surface annotated in fig. 16D below) extending from a topmost point of the first sidewall surface to a topmost point of the second sidewall surface;…See Ching at para. [0001] – [0113], figs. 1-31.
Regarding claim 17:
Ching does not show in the figures:
a silicide layer extending over the top surface of the p-type source/drain feature; and
a source/drain contact over and electrically coupled to the silicide layer.
However, it would have been obvious to one of ordinary skill in the art to form “a silicide layer extending over the top surface of the p-type source/drain feature; and a source/drain contact over and electrically coupled to the silicide layer” because Ching teaches in the description that the device undergoes further processing to form interconnection features that includes contacts and that the interconnection features may be made of silicide. See Ching at para. [0108].
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Ching further teaches:
18. The semiconductor structure of claim 17, wherein the top surface of the p-type source/drain feature (1302B) curves downward (e.g. curves downward at the trough).
19. The semiconductor structure of claim 17, wherein a distance between the topmost point of the first sidewall surface and a bottommost point of the curved top surface the p-type source/drain feature is substantially equal to a distance between the topmost point of the second sidewall surface and the bottommost point of the curved top surface the p-type source/drain feature (e.g. See fig. 16 annotated above to show d1 ~ d2.)
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Yu US 20180342583 A1. Yu teaches a source/drain with a convex top surface in fig. 13.
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
17 July 2026
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