DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 112_E found in FIG. 13C. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 13-14, 16-18, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US PGPub 20210134820 A1; hereinafter referred to as "Huang”).
Re claim 1: Huang teaches a semiconductor device, comprising: a first memory stacking pair (FIG. 1A: el. 1st semiconductor structure, 2nd semiconductor structure; para. 52, 62), comprising a first memory semiconductor structure (FIG. 1A: el. 2nd semiconductor structure; para. 62) having a first front side (FIG. 1A: el. 118; para. 62) and a first back side (FIG. 1A: el. 104; para. 62) opposite to the first front side (FIG. 1A); and a second memory semiconductor structure (FIG. 1A: el. 1st semiconductor structure; para. 52) having a second front side (FIG. 1A: el. 108; para. 52) and a second back side (FIG. 1A: el. 102; para. 52) opposite to the second front side (FIG. 1A), wherein the first memory semiconductor structure is bonded to the second memory semiconductor structure (para. 48), and the first front side of the first memory semiconductor structure is proximal to the second front side of the second memory semiconductor structure, and the first back side is distal to the second back side (FIG. 1A; para. 48).
Re claim 2: Huang teaches the semiconductor device of claim 1, further comprising: a logic semiconductor structure (FIG. 1A: el. 3rd semiconductor structure; para. 67) having a front side (FIG. 1A: el. 122; para. 67) and a back side (FIG. 1A: el. 106; para. 67), wherein the logic semiconductor structure is bonded to the first memory stacking pair (FIG. 1A; para. 67), and the front side of the logic semiconductor structure is proximal to the first back side of the first memory semiconductor structure (FIG. 1A: el. 122, 104).
Re claim 1 (second mapping): Huang teaches a semiconductor device, comprising: a first memory stacking pair (annotated FIG. 9: el. 918, 916|annotated FIG. 9 provided below labels the 1st memory stacking pair; para. 141), comprising a first memory semiconductor structure (annotated FIG. 9: el. 918; para. 141) having a first front side (annotated FIG. 9: el. 1st front side) and a first back side (annotated FIG. 9: el. 1st back side) opposite to the first front side (annotated FIG. 9); and a second memory semiconductor structure (FIG. 9: el. 916; para. 141) having a second front side (annotated FIG. 9: el. 2nd front side) and a second back side (annotated FIG. 9: el. 2nd back side) opposite to the second front side (annotated FIG. 9), wherein the first memory semiconductor structure is bonded to the second memory semiconductor structure (annotated FIG. 9: el. 918, 916; para. 141), and the first front side of the first memory semiconductor structure is proximal to the second front side of the second memory semiconductor structure (annotated FIG. 9: el. 1st front side, 2nd front side; para. 141), and the first back side is distal to the second back side (annotated FIG. 9: el. 1st back side, 2nd back side).
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Re claim 3: Huang teaches the semiconductor device of claim 1 (as per Re claim 1 (second mapping) section), further comprising: a second memory stacking pair (annotated FIG. 9: el. 914, 912|annotated FIG. 9, provided in Re claim 1 (second mapping) section, labels the 2nd memory stacking pair; para. 141), comprising a third memory semiconductor structure (annotated FIG. 9: el. 914; para. 141) having a third front side (annotated FIG. 9: el. 3rd front side) and a third back side (annotated FIG. 9: el. 3rd back side); and a fourth memory semiconductor structure (annotated FIG. 9: el. 912; para. 141) having a fourth front side (annotated FIG. 9: el. 4th front side) and a fourth back side (annotated FIG. 9: el. 4th back side); wherein the third memory semiconductor structure is bonded to the fourth memory semiconductor structure (annotated FIG. 9: el. 914, 912; para. 141), and the third front side of the third memory semiconductor structure is proximal to the fourth front side of the fourth memory semiconductor structure (annotated FIG. 9: el. 3rd front side, 4th front side; para. 141).
Re claim 4: Huang teaches the semiconductor device of claim 3, wherein the first memory stacking pair is bonded to the second memory stacking pair (annotated FIG. 9: el. 1st memory stacking pair, 2nd memory stacking pair; para. 141|annotated FIG. 9, provided in Re claim 1 (second mapping) section, labels 1st and 2nd memory stacking pairs), and the second back side of the second memory semiconductor structure is proximal to the third back side of the third memory semiconductor structure (annotated FIG. 9: el. 2nd back side, 3rd back side; para. 141).
Re claim 5: Huang teaches the semiconductor device of claim 4, further comprising: a logic semiconductor structure (annotated FIG. 9: el. 920) having a front side and a back side (annotated FIG. 9, provided in Re claim 1 (second mapping) section, labels front and back sides of logic structure), wherein the logic semiconductor structure is bonded to the first memory stacking pair (annotated FIG. 9: el. 920, 1st memory stacking pair; para. 141), and the front side of the logic semiconductor structure is proximal to the first back side of the first memory semiconductor structure (annotated FIG. 9: el. front side of logic structure, 1st back side).
Re claim 13: A semiconductor device, comprising: N memory stacking pairs (annotated FIG. 9: el. 1st memory stack pair, 2nd memory stacking pair| annotated FIG. 9, provided in Re claim 1 (second mapping) section, labels 1st and 2nd memory stacking pairs of the N memory stacking pairs), each of the N memory stacking pairs comprising a first memory semiconductor structure (annotated FIG. 9: el. 918; para. 141) having a first front side and a first back side opposite to the first front side (annotated FIG. 9: el. 1st front side, 1st back side); and a second memory semiconductor structure (annotated FIG. 9: el. 918; para. 141) having a second front side and a second back side opposite to the second front side (annotated FIG. 9: el. 2nd front side, 2nd back side), wherein N≥1 (at least one memory stacking pair is present in the semiconductor device), and the first memory semiconductor structure is bonded to the second memory semiconductor structure (annotated FIG. 9; para. 141) with the first front side of the first memory semiconductor structure being proximal to the second front side of the second memory semiconductor structure (annotated FIG. 9: el. 1st front side, 2nd front side), and the first back side being distal to the second back side.
Re claim 14: The semiconductor of the claim 13, wherein: a first memory stacking pair of the N memory stacking pairs is bonded to a second memory stacking pair of the N memory stacking pairs, and a back side of a memory semiconductor structure in the first memory stacking pair is proximal to a back side of a memory semiconductor structure in the second memory stacking pair (annotated FIG. 9, provided in Re claim 1 (second mapping) section, shows 1st memory stacking pair bonded to 2nd memory stacking pair; para. 141).
Re claim 16: A method of manufacturing a semiconductor device, comprising: providing a first memory semiconductor structure having a first front side and a first back side (FIG. 5A: el. 2nd semiconductor structure, FIG. 13: el. 1302; para. 100); providing a second memory semiconductor structure having a second front side and a second back side (FIG. 5A: el. 1st semiconductor structure, FIG. 13: el. 1302; para. 100); and bonding the first memory semiconductor structure to the second memory semiconductor structure to form a first memory stacking pair, wherein the first front side of the first memory semiconductor structure is proximal to the second front side of the second memory semiconductor structure (FIG. 5B: el. 1st semiconductor structure, 2nd semiconductor structure, FIG. 13: el. 1304; para. 100).
Re claim 17: The method of claim 16, further comprising: providing a logic semiconductor structure having a front side and a back side (FIG. 5D-5E: el. 3rd semiconductor structure; FIG. 13: el. 1308; para. 121-122); and bonding the logic semiconductor structure to the first memory stacking pair, wherein the front side of the logic semiconductor structure is proximal to the first back side of the first memory semiconductor structure (FIG. 5E: el. 3rd semiconductor structure, 1st semiconductor structure; FIG. 13: el. 1308; para. 121-122).
Re claim 18: The method of claim 16, further comprising: providing a third memory semiconductor structure having a third front side and a third back side (FIG. 9: el. 914, FIG. 14: el. 1402; para. 141-145); providing a fourth memory semiconductor structure having a fourth front side and a fourth back side (FIG. 9: el. 912, FIG. 14: el. 1402; para. 141-145); and bonding the third memory semiconductor structure to the fourth memory semiconductor structure to form a second memory stacking pair (FIG. 9: el. 914, 912, FIG. 14: el. 1402; para. 141-145), wherein the third front side of the third memory semiconductor structure is proximal to the fourth front side of the fourth memory semiconductor structure (FIG. 9: el. 914, 912); and bonding the first memory stacking pair to the second memory stacking pair (FIG. 9: el. (918, 916), (914, 912), FIG. 14: el. 1404), wherein the second back side of the second memory semiconductor structure is proximal to the third back side of the third memory semiconductor structure (FIG. 9: el. 916, 914).
Re claim 20: The method of claim 18, further comprising: providing a logic semiconductor structure having a front side and a back side (FIG. 9: el. 920, FIG. 14: el. 1408; para. 141); and bonding the logic semiconductor structure to the first memory stacking pair, after the bonding the first memory stacking pair to the second memory stacking pair (FIG. 14: el. 1408; para. 150).
Claims 1, 6, 12, 13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bhushan et al. (US PGPub 20240297149 A1; hereinafter referred to as "Bhushan”).
Re claim 1: Bhushan teaches a semiconductor device, comprising: a first memory stacking pair (annotated FIG. 2: 1st memory stacking pair| annotated FIG. 2, provided below, labels the 1st memory stacking pair), comprising a first memory semiconductor structure (annotated FIG. 2: el. 208; para. 21) having a first front side (annotated FIG. 2: el. 1st front side; para. 21) and a first back side (annotated FIG. 2: el. 1st back side; para 21) opposite to the first front side; and a second memory semiconductor structure (annotated FIG. 2: el. 210; para. 21) having a second front side (annotated FIG. 2: el. 2nd front side; para. 21) and a second back side (annotated FIG. 2: 2nd back side; para. 21) opposite to the second front side, wherein the first memory semiconductor structure is bonded to the second memory semiconductor structure (annotated FIG. 2: el. 208, 210; para. 20-21), and the first front side of the first memory semiconductor structure is proximal to the second front side of the second memory semiconductor structure, and the first back side is distal to the second back side (annotated FIG. 2: el. 1st front side, 2nd front side, 1st back side, 2nd back side; para. 20-21).
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Re claim 6: The semiconductor device of claim 1, further comprising: a fifth memory semiconductor structure (annotated FIG. 2: el. 206; para. 20) having a fifth front side and a fifth back side (annotated FIG. 2: el. 5th front side, 5th back side; para. 20-21| annotated FIG. 2, provided directly above in Re claim 1 section, labels the 5th front and back sides); wherein the fifth memory semiconductor structure is bonded to the first memory stacking pair (annotated FIG. 2: el. 206, 208, 1st memory stacking pair; para. 20-21), and the fifth front side of the fifth memory semiconductor structure is proximal to the first back side of the first memory semiconductor structure (annotated FIG. 2: el. 5th front side, 1st back side; para. 20-21).
Re claim 12: The semiconductor device of claim 1, wherein: the first memory semiconductor structure and the second memory semiconductor structure are dynamic-random-access-memory (para. 18, 35).
Re claim 13: A semiconductor device, comprising: N memory stacking pairs (annotated FIG. 2: 1st memory stacking pair| annotated FIG. 2, provided above in Re claim 1 section, labels the 1st memory stacking pair), each of the N memory stacking pairs comprising a first memory semiconductor structure (annotated FIG. 2: el. 208; para. 21) having a first front side and a first back side opposite to the first front side (annotated FIG. 2: el. 1st front side, 1st back side; para. 21); and a second memory semiconductor structure (annotated FIG. 2: el. 210; para. 21) having a second front side and a second back side opposite to the second front side (annotated FIG. 2: 2nd front side, 2nd back side; para. 21), wherein N≥1 (at least one memory stacking pair is present in the semiconductor device), and the first memory semiconductor structure is bonded to the second memory semiconductor structure (annotated FIG. 2: el. 208, 210; para. 20-21) with the first front side of the first memory semiconductor structure being proximal to the second front side of the second memory semiconductor structure, and the first back side being distal to the second back side (annotated FIG. 2: el. 1st front side, 2nd front side, 1st back side, 2nd back side; para. 20-21).
Re claim 15: The semiconductor of the claim 13, further comprising: M single memory semiconductor structures (annotated FIG. 2: el. 206; para. 20) stacked with the N memory stacking pairs (annotated FIG. 2: 1st memory stacking pair| annotated FIG. 2, provided above in Re claim 1 section, labels the 1st memory stacking pair), and M≥1 (at least one single memory semiconductor structure is present in the semiconductor device), wherein one of the M single memory semiconductor structures is bonded to one of the N memory stacking pairs (annotated FIG. 2: el. 5th memory semiconductor structure, 1st memory stacking pair; para. 20-21), and the one of the M single memory semiconductor structures comprises a substrate and a front side distal to the substrate (annotated FIG. 2: el. 5th substrate, 5th front side; para. 20-21), wherein the front side of the one of the M single memory semiconductor structures is proximal to a back side of a memory semiconductor structure in the one of the N memory stacking pairs (annotated FIG. 2: el. 5th front side, 1st back side).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 1 above, and further in view of Bhushan.
Re claim 6: Huang fails to teach semiconductor device of claim 1, further comprising: a fifth memory semiconductor structure having a fifth front side and a fifth back side; wherein the fifth memory semiconductor structure is bonded to the first memory stacking pair, and the fifth front side of the fifth memory semiconductor structure is proximal to the first back side of the first memory semiconductor structure.
In a similar field of endeavor, Bhushan teaches memory semiconductor structures stacked on a logic chip, wherein the memory semiconductor structure stacks have an odd number of memory semiconductor structures. Bhushan teaches a three-layer memory semiconductor stack (FIG. 2: el. 202; para. 18), including a 1st memory semiconductor pair (FIG. 2: el. 208, 210; para. 21|1st memory semiconductor structure 208 bonded to 2nd memory semiconductor structure 210 by front-to-front bonding) on a single memory semiconductor structure (FIG. 2: el. 206), which is formed as a memory semiconductor stack that is sorted by known-good stacks and subsequently bonded to a semiconductor structure (para. 27-29). Bhushan teaches a fifth memory semiconductor structure (annotated FIG. 2: el. 206) having a fifth front side and a fifth back side (annotated FIG. 2, provided below, labels the 5th front side and the 5th back side of the fifth memory semiconductor structure); wherein the fifth memory semiconductor structure is bonded to the first memory stacking pair (annotated FIG. 2: el. 206, 1st memory stacking pair), and the fifth front side of the fifth memory semiconductor structure is proximal to the first back side of the first memory semiconductor structure (annotated FIG. 2: el. 5th front side, 1st back side). Bhushan also teaches including more memory semiconductor structures such that the memory stack could equal 5 memory semiconductor dies (para. 22). Bhushan further teaches a benefit of stacking multiple dies on top of one another is an increase in the number of circuit elements of a package without increasing the package footprint (para. 9).
A person of ordinary skill in the art, seeking to increase the memory capacity of a semiconductor package without increasing the footprint of the package, would have been motivated to combine the 3-layer memory semiconductor stack of Bhushan with the 2-layer 1st memory stacking pair of the semiconductor device of Huang by bonding a known-good 3-layer memory semiconductor stack, as taught by Bhushan, to the 1st memory stacking pair (Huang - FIG. 1A: el. 1st semiconductor structure, 2nd semiconductor structure) of Huang, for the benefit of an increased memory capacity of a 5-layer memory semiconductor stack without an increased footprint of the semiconductor device.
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Re claim 8: The combination of Huang and Bhushan teaches the semiconductor device of claim 6, further comprising a second memory stacking pair (annotated FIG. C: el. 2nd memory stacking pair| annotated FIG. C, provided below, shows the combination of Bhushan and Huang discussed in Re claim 6 section), bonded to the fifth back side of the fifth memory semiconductor structure (annotated FIG. C: el. 5th back side).
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Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Bhushan as applied to claim 6 above (refer to Re claim 6 section of §102).
Re claim 7: Bhushan teaches the semiconductor device of claim 6, further comprising a logic semiconductor structure having a front side and a back side (annotated FIG. 2: el. 204; para. 18), wherein the logic semiconductor structure is bonded to the fifth memory semiconductor structure (annotated FIG. 2: el. 5th memory semiconductor structure; para. 18-19| annotated FIG. 2, provided below, labels the 5th memory semiconductor structure), and the logic semiconductor structure is proximal to the fifth back side of the fifth memory semiconductor structure (annotated FIG. 2: el. 204, 5th memory semiconductor structure). All of the claimed elements are provided by Bhushan except for the orientation of the logic semiconductor structure, wherein the front side of the logic semiconductor structure is proximal to the fifth back side of the fifth memory semiconductor structure. One of ordinary skill in the art would have recognized the finite number of predictable solutions for the two possible orientations of a logic structure connected to a memory stack. Absent unexpected results, it would have been obvious to try each of the two possible orientations consisting of a front side of the logic structure facing the memory stack structure and a back side of the logic structure facing the memory stack structure to yield a logic semiconductor structure effectively bonded to a memory semiconductor structure.
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Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 1 above, and further in view of Lee et al. (US PGPub 20240030103 A1; hereinafter referred to as "Lee”).
Re claim 9: Huang is silent to the semiconductor device of claim 1, wherein: a circuitry layout of the first memory semiconductor structure is identical to a circuitry layout of the second memory semiconductor structure, and the layout of the first memory semiconductor structure is mirror symmetric.
In a similar field of endeavor, Lee teaches a semiconductor device comprising a semiconductor chip stack with identical and symmetric electrode layouts in adjacent chips. Lee teaches a semiconductor device, wherein: a circuitry layout (FIG. 4: el. 140A, 150A; para. 28-29) of the first memory semiconductor structure (FIG. 4: el. 100A; para. 71) is identical (FIG. 4: el. 140, 150; para. 27) to a circuitry layout (FIG. 4: el. 140B, 150B; para. 28-29) of the second memory semiconductor structure, and the layout of the first memory semiconductor structure is mirror symmetric (FIG. 4: el. 140, 150|electrode layout of the first memory semiconductor structure 100A is mirror symmetric). Lee also teaches a benefit of a symmetric electrode circuit layout being matched in adjacent stacked chips is that an electrical interconnection path between the chips can be formed even with different stacking arrangements (para. 27, FIG. 4, FIG. 1A, FIG. 3).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Huang and Lee, to enable using circuitry layout of adjacent stacked chips of Lee in the semiconductor device of Huang, for the benefit of forming an electrical interconnection path between adjacent bonded chips.
Re claim 10: The combination of Huang and Lee teaches the semiconductor device of claim 1, wherein: a circuitry layout of the first memory semiconductor structure is a mirror image of a circuitry layout of the second memory semiconductor structure (Lee - FIG. 4; para. 26|electrode layout of 140, 150 of first memory semiconductor structure 100A is a mirror image of electrode layout 140, 150 of second memory semiconductor structure 100B).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 1 above, and further in view of Chen et al. (US PGPub 20220059455 A1; hereinafter referred to as "Chen”).
Re claim 11: Huang fails to teach the semiconductor device of claim 1, wherein: the first stacking memory pair comprises a RDL formed on the first back side of the first memory semiconductor structure.
In a similar field of endeavor, Chen teaches a memory pair comprising an RDL formed on a back side of the memory pair. Chen teaches a first stacking memory pair (FIG. 11A: el. 201a, 201b; para. 71, 36) comprising a RDL (FIG. 11A: el. 200; para. 36, 71|interface structure 200 formed of redistribution interconnection lines functions as a redistribution layer (RDL)) formed on the first back side of the first memory semiconductor structure (FIG. 11A: el. 201a; para. 71). Chen also teaches that a benefit of forming a RDL on the memory pair is an increase in the memory bandwidth by utilizing the vertical direction, as opposed to the lateral direction, for integrating the interconnection wiring (para. 36).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Huang and Chen, to enable using the RDL of Chen on the memory pair of the semiconductor device of Huang, for the benefit of increasing memory bandwidth of the semiconductor device.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 1 above, and further in view of Vodrahalli et al. (US PGPub 20210104495 A1; hereinafter referred to as "Vodrahalli”).
Re claim 19: Huang teaches the method of claim 18, wherein the step of bonding the first memory stacking pair to the second memory stacking pair comprises: thinning a substrate at the second back side of the second memory semiconductor structure (para. 149); thinning a substrate at the third back side of the third memory semiconductor structure (para. 149). Huang fails to teach forming a bonding layer over the substrate of the second memory semiconductor structure; forming a bonding layer over the substrate of the third memory semiconductor structure; and bonding the bonding layer over the substrate of the second memory semiconductor structure to the bonding layer over the substrate of the third memory semiconductor structure.
In a similar field of endeavor, Vodrahalli teaches thinning a substrate at the backside of a memory semiconductor structure of a memory stacking pair (FIG. 8; para. 56) followed by forming a bonding layer over the substrate (FIG. 9: el. 142; para. 57) and subsequently by bonding the bonding layer of a memory stacking pair to the bonding layer of another memory stacking pair (FIG. 22; para. 77). Vodrahalli teaches forming a bonding layer over the substrate of the second memory semiconductor structure (FIG. 9: el. 142; para. 77|annotated FIG. 22, provided below, labels the bond pads 142a over the substrate of the second memory structure); forming a bonding layer over the substrate of the third memory semiconductor structure (FIG. 9: el. 142; para. 77|annotated FIG. 22, provided below, labels the bond pads 142b over the substrate of the third memory structure); and bonding the bonding layer over the substrate of the second memory semiconductor structure to the bonding layer over the substrate of the third memory semiconductor structure (annotated FIG. 22: el. 142a, 142b). Vodrahalli also teaches a benefit of the bonding layer is to enable an electrical connection between conductive features of the 1st and 2nd memory stacking pairs (para. 78).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Huang and Vodrahalli, to enable using formation of a bonding layer on the 1st and 2nd memory stacking pairs of Vodrahalli in the method of manufacturing a semiconductor device of Huang, for the benefit of enabling an electrical connection between the 1st and 2nd memory stacking pairs.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights