Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/777,454 filed on July 18, 2024.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Objections
5. Claims 19-20 are objected to because of the following informalities: In the following, the claims should be recited to smooth flow of claim languages/phrases by avoiding ‘the’ before gerund:
19. (Currently Amended) The method according to claim 18,
wherein
wherein
20. (Currently Amended) The method according to claim 18, further comprising directly forming a power line or a sub-gate line on the silicon substrate,
wherein
connecting the second active pattern and the power line to each other; or
connecting the second active pattern and the sub-gate line to each other.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claim 15 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Youn et al. (US 2021/0159298 A1).
Regarding independent claim 15, Youn et al. teaches a sub-pixel (PX, para [0062]) comprising (Figs. 1-2):
a light emitting element (200, para [0062]); and
a sub-pixel circuit (comprising transistors T1 and T2, para [0077]) configured to supply a current to the light emitting element (200) (the underline limitation is a functional limitation/an intended use), wherein the sub-pixel circuit comprises:
a driving transistor (T1) comprising a first active pattern (ACT1) having a single-crystalline structure (polycrystalline silicon, para [0065]) on a silicon substrate (100) and connected to a first node and a third node, and a first gate electrode (GE1) connected to a second node and comprising at least a portion overlapping with the first active pattern (ACT1), the driving transistor (T1) being configured to provide a current corresponding to a voltage applied to the second node (the underline limitation is a functional limitation/an intended use); and
a compensation transistor (T2) comprising a second active pattern (ACT2) comprising a metal oxide semiconductor layer (para [0071]), and a second gate electrode (GE2) comprising at least a portion overlapping with the second active pattern (ACT2), the compensation transistor (T2) being configured to switch an electrical connection between the first node and the second node (the underline limitation is a functional limitation/an intended use).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
12. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
13. Claims 1-2, 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Youn et al. (US 2021/0159298 A1) in view of Takagi (US 6,339,232 B1).
Regarding independent claim 1, Youn et al. teaches a display panel comprising (Fig. 2):
a substrate (100, para [0062]);
a first active pattern (ACT1, para [0064]) comprising a single-crystalline semiconductor layer (polycrystalline silicon, para [0065]) on the substrate (100);
a first gate insulating layer (120, para [0066]) covering the first active pattern (ACT1);
a first gate electrode (GE1, para [0067]) on the first gate insulating layer (120), and comprising at least a portion overlapping with the first active pattern (ACT1);
a first interlayer insulating layer (130, para [0068]) on the first gate electrode (GE1);
a second active pattern (ACT2, para [0071]) on the first interlayer insulating layer (130), and comprising a metal oxide semiconductor (ITO, para [0071]);
a second gate insulating layer (160, para [0072]) covering the second active pattern (ACT2);
a second gate electrode (GE2, para [0072]) on the second gate insulating layer (160), and comprising at least a portion overlapping with the second active pattern (ACT2);
a second interlayer insulating layer (150, para [0074]) covering the second gate electrode (GE2); and
a source/drain electrode layer (DE1/SE1/DE2/SE2) on the second interlayer insulating layer (150), and connected to the first and second active patterns (ACT1/ACT2).
Youn et al. is explicitly silent of disclosing wherein, the substrate is made of silicon material.
Takagi teaches wherein (Fig. 2A), the substrate (2) is made of silicon material (col. 8, lines 63-64).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Takagi, and substitute w/silicon material of the substrate material of Youn et al., in order to having stable device and ensuring excellent performance for standard computing and memory applications.
Regarding claim 2, Youn et al. and Takagi teach all of the limitations of claim 1 from which this claim depends.
The combination of Youn et al. and Takagi teaches wherein, the first active pattern (ACT1, see Fig. 2) is located on the buffer layer (110); the silicon substrate (100) comprises the buffer layer (110, para [0064])
Youn et al. is explicitly silent of disclosing wherein, the buffer layer comprising silicon oxide.
Takagi teaches wherein (Fig. 2b), the buffer layer (6) comprising silicon oxide (col. 9, lines 34-37).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Takagi, and modify the buffer layer with silicon dioxide material of Youn et al., in order to having an electrical insulator, stability at high temperatures, and compatibility with silicon and ensure an excellent performance semiconductor device.
Regarding independent claim 17, Youn et al. teaches a method of fabricating a display panel, comprising (Figs. 1-2):
forming a first active pattern (ACT1, para [0064]) having a single-crystalline structure (polycrystalline silicon, para [0065]) on a substrate (100, para [0063]);
forming a first gate insulating layer (120, para [0066]) on the first active pattern (ACT1);
forming a first gate electrode (GE1, para [0067]) comprising at least a portion overlapping with the first active pattern (ACT1);
forming a first interlayer insulating layer (130, para [0068]) on the first gate electrode (GE1);
forming a second active pattern (ACT2, para [0071]) comprising a metal oxide semiconductor (ITO, para [0071]) on the first interlayer insulating layer (130);
forming a second gate insulating layer (160, para [0072]) on the second active pattern (ACT2);
forming, on the second gate insulating layer (160), a second gate electrode (GE2, para [0072]) comprising at least a portion overlapping with the second active pattern (ACT2);
forming a second interlayer insulating layer (150, para [0074]) on the second gate electrode (GE2); and
forming, on the second interlayer insulating layer (150), a source/drain electrode layer (DE1/SE1/DE2/SE2) connected to the first and second active patterns.
Youn et al. is explicitly silent of disclosing wherein, the substrate is made of silicon material.
Takagi teaches wherein (Fig. 2A), the substrate (2) is made of silicon material (col. 8, lines 63-64).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Takagi, and substitute w/silicon material of the substrate material of Youn et al., in order to having stable device and ensuring excellent performance for standard computing and memory applications.
Regarding claim 18, Youn et al. and Takagi teach all of the limitations of claim 17 from which this claim depends.
Youn et al. teaches wherein (Fig. 2), the first active pattern (ACT1) is formed on the buffer layer (110).
Youn et al. is explicitly silent of disclosing wherein, further comprising forming a buffer layer (110) by injecting oxygen ions into the silicon substrate.
Takagi teaches wherein (Figs. 2a-b), forming the buffer layer (15/16) by injecting (SIMOX method, see col. 9, lines 30-40) oxygen ions into the silicon substrate (2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Takagi, and apply the process step while forming the buffer layer of Youn et al., in order to obtain better electrical isolation, higher heat tolerance and precise control.
14. Claims 3-14, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Youn et al. (US 2021/0159298 A1) in view of Takagi (US 6,339,232 B1) as applied to claim 1 above, and further in view of Kim et al. (US 2021/0050398 A1).
Regarding claim 3, Youn et al. and Takagi teach all of the limitations of claim 1 from which this claim depends.
Youn et al. and Takagi are explicitly silent of disclosing wherein, the first active pattern is part of a semiconductor of a P-type transistor, and the second active pattern is part of a semiconductor of an N-type transistor.
Kim et al. teaches wherein (Fig. 4), the first active pattern (AR1) is part of a semiconductor of a P-type transistor (PMOS, para [0101]), and the second active pattern (AR2) is part of a semiconductor of an N-type transistor (para [0101]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Kim et al., and apply to the circuitrys of Youn et al. and Takagi, in order to drive the current to the LED and generate light by recombining electrons and holes.
Regarding claim 4, Youn et al. teaches wherein (Figs. 1-2), at least one light emitting element (200), wherein at least one of the plurality of sub-pixels further comprises:
a driving transistor (T1, para [0077]) comprising a semiconductor layer, a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node, the driving transistor (T1) being configured to control a magnitude of a current flowing through the light emitting element based on a voltage applied to the second node (the underline limitation is a functional limitation/an intended use); and
a compensation transistor (T2) comprising a semiconductor layer, and configured to switch an electrical connection between the first node and the second node (the underline limitation is a functional limitation/an intended use), and
wherein the semiconductor layer (ACT1) of the driving transistor comprises the first active pattern, and the semiconductor layer (ACT2) of the compensation transistor comprises the second active pattern.
Youn et al. and Takagi are explicitly silent of disclosing wherein, the display panel comprises a plurality of sub-pixels.
Kim et al. discloses wherein (Fig. 1), the display panel (display region, DA) comprises a plurality of sub-pixels (pixels, para [0067]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Kim et al., and having plurality of pixels or sub-pixels to the display panel of Youn et al. and Takagi, in order to arrange a matrix form or shape that enhances the brightness of the display panel.
Regarding claim 5, Youn et al. and Takagi and Kim et al. teach all of the limitations of claim 1 from which this claim depends.
Kim et al. teaches wherein (Fig. 3), a gate electrode of the compensation transistor (T3) is connected to a sub-gate line (Gw-n).
Regarding claim 6, Youn et al. and Takagi and Kim et al. teach all of the limitations of claim 5 from which this claim depends.
Kim et al. teaches wherein (Fig. 3), the sub-gate line comprises the source/drain electrode layer.
Regarding claim 7, Youn et al. and Takagi and Kim et al. teach all of the limitations of claim 5 from which this claim depends.
The combination of Youn et al. and Takagi and Kim et al. teaches, wherein the sub-gate line (Gw-n) is directly located on the silicon substrate (101), and
wherein the source/drain electrode layer comprises a connection electrode configured to electrically connect the sub-gate line and the second active pattern to each other.
Regarding claim 8, Youn et al. and Takagi and Kim et al. teach all of the limitations of claim 4 from which this claim depends.
Kim et al. teaches wherein (Fig. 3), the at least one of the plurality of sub-pixels further comprises an initialization transistor (T7, para [0085]) comprising a semiconductor layer, and configured to switch an electrical connection between the second node and a power line configured to be applied with an initialization voltage (the underline limitation is a functional limitation/an intended use), and
wherein the semiconductor layer (NMOS material) of the initialization transistor (T7) comprises the second active pattern.
Regarding claim 9, Youn et al. and Takagi and Kim et al. teach all of the limitations of claim 8 from which this claim depends.
Kim et al. teaches wherein (Fig. 3), a gate electrode of the initialization transistor (T7) is connected to a sub-gate line.
Regarding claim 10, Youn et al. and Takagi and Kim et al. teach all of the limitations of claim 8 from which this claim depends.
Kim et al. teaches wherein (Fig. 3), the sub-gate line comprises the source/drain electrode layer.
Regarding claim 11, Youn et al. and Takagi and Kim et al. teach all of the limitations of claim 8 from which this claim depends.
The combination of Youn et al. and Takagi and Kim et al. teaches wherein, the sub-gate line is directly located on the silicon substrate (100), and
wherein the source/drain electrode layer comprises a connection electrode configured to electrically connect the sub-gate line and the second active pattern to each other.
Regarding claim 12, Youn et al. and Takagi and Kim et al. teach all of the limitations of claim 8 from which this claim depends.
Kim et al. teaches wherein (Fig. 4), the source/drain electrode layer (152) comprises a first source/drain electrode layer, and
wherein the display panel (DA) comprises:
a first via layer (VIA1, para [0158]) covering the first source/drain electrode layer (152);
a second source/drain electrode layer (161) on the first via layer (VIA1), and connected to the first source/drain electrode layer (152) through a contact hole (CNT2, para [0112]); and
a second via layer (VIA2, para [0159]) covering the second source/drain electrode layer (161).
Regarding claim 13, Youn et al. and Takagi and Kim et al. teach all of the limitations of claim 12 from which this claim depends.
Kim et al. teaches wherein (Fig. 4), the power line (1st power voltage ELVDD, para [0087]) comprises the second source/drain electrode layer (161).
Regarding claim 14, Youn et al. and Takagi and Kim et al. teach all of the limitations of claim 8 from which this claim depends.
Youn et al. and Takagi and Kim et al. teaches wherein, the power line is directly located on the silicon substrate (100), and
wherein the source/drain electrode layer (151/152) comprises a connection electrode (165) configured to electrically connect the power line (ELVDD) and the second active pattern (135) to each other.
Regarding claim 19, Youn et al. and Takagi teach all of the limitations of claim 18 from which this claim depends.
Youn et al. and Takagi are explicitly silent of disclosing wherein, forming of the first active pattern comprises doping a P-type impurity, and
wherein forming of the second active pattern comprises doping an N-type impurity.
Kim et al. teaches wherein (Fig. 4), the first active pattern (AR1) is part of a semiconductor of a P-type transistor (PMOS, para [0101]) (therefore, it is considered that the first active pattern is doped with p-type material), and the second active pattern (AR2) is part of a semiconductor of an N-type transistor (para [0101] therefore, it is considered that the second active pattern is doped with n-type material).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Kim et al., and apply to the circuitrys of Youn et al. and Takagi, in order to drive the current to the LED and generate light by recombining electrons and holes.
Regarding claim 20, Youn et al. and Takagi teach all of the limitations of claim 18 from which this claim depends.
Youn et al. teaches wherein (Fig. 1), further comprising directly forming a power line (PL, para [0045]) or a sub-gate line on the silicon substrate (100),
wherein forming of the source/drain electrode layer (DE1/SE1/DE2/SE2) comprises at least one of:
connecting the second active pattern (ACT2) and the power line (PL) to each other; or
connecting the second active pattern (ACT2) and the sub-gate line to each other.
15. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Youn et al. (US 2021/0159298 A1) as applied to claim 15 above, and further in view of Kim et al. (US 2021/0050398 A1).
Regarding claim 16, Youn et al. teaches all of the limitations of claim 15 from which this claim depends.
Youn et al. is explicitly silent of disclosing wherein, the first active pattern is part of a semiconductor of a P-type transistor, and the second active pattern is part of a semiconductor of an N-type transistor.
Kim et al. teaches wherein (Fig. 4), the first active pattern (AR1) is part of a semiconductor of a P-type transistor (PMOS, para [0101]), and the second active pattern (AR2) is part of a semiconductor of an N-type transistor (para [0101]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Kim et al., and apply to the circuitrys of Youn et al., in order to drive the current to the LED and generate light by recombining electrons and holes.
Examiner’s Note
16. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
18. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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