DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8 & 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US 20250120101) in view of Paranjpe et al. (US 20060128139).
Regarding claim 1, Ho discloses that a metal-insulator-metal (MIM) capacitor structure, comprising:
a substrate 101;
a recess 402 disposed in the substrate, wherein the recess comprises a sidewall and a bottom;
a pillar 412-415 disposed in the recess and contacting the bottom of the recess, wherein the pillar is formed by stacking a silicon nitride-based material layer or a silicon oxide-based material layer cyclically and alternately (para. 0040), the silicon oxide-based material layer 412 comprises a first sidewall (Fig. 4D); and an MIM capacitor continuously covering and contacting the pillar, the sidewall of the recess and the bottom of the recess (Fig. 4D).
Ho fails to teach that the pillar is formed by stacking a silicon nitride-based material layer and a silicon oxide-based material layer and the first side wall has an arc-profile.
However, Paranjpe suggests that a pillar is formed by stacking a silicon nitride-based material layer and a silicon oxide-based material layer (para. 0003, note: ONO) and the first side wall has an arc-profile (at a top & a bottom of ONO layers).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Ho with a pillar is formed by stacking a silicon nitride-based material layer and a silicon oxide-based material layer and the first side wall has an arc-profile as taught by Paranjpe in order to enhance a barrier, to prevent migration (para. 0035) and also, the claim would have been obvious because the substitution of one know element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention.
Reclaim 2, Ho & Paranjpe disclose that the arc-shaped profile is concave toward the center of the pillar (Fig. 3, Paranjpe).
Reclaim 3, Ho & Paranjpe disclose that the silicon nitride-based material layer has a second sidewall, and the second sidewall is a flat surface (Fig. 3, Paranjpe, a middle portion) .
Reclaim 4, Ho & Paranjpe disclose that a plurality of the pillars disposed in the recess and contacting the bottom of the recess, wherein the MIM capacitor continuously covers and contacts the plurality of pillars (note: can be plurality of capacitor in a wafer).
Reclaim 5, Ho & Paranjpe fail to specify that a thickness of the bottommost silicon nitride-based material layer is greater than a thickness of the bottommost silicon oxide-based material layer.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of the bottommost silicon nitride-based material layer and a thickness of the bottommost silicon oxide-based material layer because it would have been to obtain a certain thickness of the bottommost silicon nitride-based material layer and a thickness of the bottommost silicon oxide-based material layer to achieve variation of dielectric property.
Reclaim 6 , Ho & Paranjpe disclose that thickness of the bottommost silicon nitride-based material layer and a thickness of the bottommost silicon oxide-based material layer the silicon oxide-based material layer and the silicon nitride-based material layer are alternately stacked to form a plurality of silicon oxide-based material layers and a plurality of silicon nitride-based material layers (Fig. 3, Paranjpe).
Ho & Paranjpe fail to specify that a thickness of each of the plurality of silicon oxide-based material layers is different.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of each of the plurality of silicon oxide-based material layers, because it would have been to obtain a certain thickness of each of the plurality of silicon oxide-based material layers to achieve variation of charge holding due to devices.
Reclaim 7, Ho & Paranjpe disclose that a dielectric layer filling 500 in the recess, covering the MIM capacitor and a top surface of the substrate (Fig. 4D, Ho).
Reclaim 8, Ho & Paranjpe disclose that the MIM capacitor comprises: a first electrode 411, a capacitor dielectric layer 412 and a second electrode 415 stacked from bottom to top in sequence (Fig. 4D, Ho).
Regarding claim 14, Ho & Paranjpe disclose that a fabricating method of a metal-insulator-metal (MIM) capacitor, comprising:
providing a substrate 401;
etching the substrate to form a recess (Paranjpe, para. 0011), wherein the recess comprises a sidewall and a bottom (Fig. 4D, Ho in view of Paranjpe);
forming a silicon nitride-based material layer and a silicon oxide-based material layer stacked cyclically and alternately to form a composite layer, wherein the composite layer covers the sidewall of the recess and the bottom of the recess; patterning the composite layer to form at least one pillar (Fig. 3, Paranjpe);
performing a selective etching to etch the silicon oxide-based material layer of the pillar ( a top portion of Fig. 3, Paranjpe); and after the selective etching, forming an MIM capacitor to continuously cover and contact the pillar, the sidewall of the recess, the bottom of the recess and a top surface of the substrate (Ho’s Fig. 4D in view of Paranjpe’s Fig. 3).
Reclaim 15, Ho & Paranjpe disclose that the selective etching comprises a chemical oxide removal (COR) process or a wet etching (para. 0011, Paranjpe).
Reclaim 16, Ho & Paranjpe disclose that after the selective etching, a sidewall of the silicon oxide-based material layer forms an arc-shaped profile which is concave toward the center of the pillar (Ho’s Fig. 4D in view of Paranjpe’s Fig. 3).
Reclaim 17, Ho & Paranjpe disclose that before patterning the composite layer, the composite layer is planarized to make a top surface of the composite layer to be aligned with the top surface of the substrate (Ho’s Fig. 4D in view of Paranjpe’s Fig. 3).
Reclaim 18, Ho & Paranjpe fail to specify that a thickness of the bottommost silicon nitride-based material layer is greater than a thickness of the bottommost silicon oxide-based material layer.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of the bottommost silicon nitride-based material layer and a thickness of the bottommost silicon oxide-based material layer because it would have been to obtain a certain thickness of the bottommost silicon nitride-based material layer and a thickness of the bottommost silicon oxide-based material layer to achieve variation of dielectric property.
Reclaim 19, Ho & Paranjpe disclose that the composite layer comprises a plurality of silicon oxide-based material layers and a plurality of silicon nitride-based material layers.
Ho & Paranjpe fail to specify that a thickness of each of the plurality of silicon oxide-based material layers is different.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of each of the plurality of silicon oxide-based material layers, because it would have been to obtain a certain thickness of each of the plurality of silicon oxide-based material layers to achieve variation of charge holding due to devices.
Reclaim 20, Ho & Paranjpe disclose that after forming the MIM capacitor, a dielectric layer 500 is formed to fill the recess and cover the MIM capacitor and the top surface of the substrate (Ho, Fig. 4D).
Allowable Subject Matter
Claims 9-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/SU C KIM/ Primary Examiner, Art Unit 2899
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