Prosecution Insights
Last updated: October 01, 2026
Application No. 18/777,584

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §112
Filed
Jul 19, 2024
Priority
May 23, 2024 — TW 113119089
Examiner
RAMALLO, GUSTAVO G
Art Unit
Tech Center
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
556 granted / 584 resolved
+35.2% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
41 currently pending
Career history
592
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
53.0%
+13.0% vs TC avg
§102
28.7%
-11.3% vs TC avg
§112
15.4%
-24.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 584 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on July 24, 2024 Information Disclosure Statement The information disclosure statement (IDS) submitted on July 19, 2024 is being considered by the examiner. . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Semiconductor Device With Two-Dimensional Channel and Method for Fabricating the Same Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the device units" in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the plurality of device units” Claim 7 recites the limitation "the openings" in line 4. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the plurality of openings” Claim 7 recites the limitation "the device units" in lines 5-6. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the plurality of device units” Claim 7 recites the limitation "the recesses" in lines 9-10. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the plurality of recesses” Allowable Subject Matter Claims 1-12 would be allowed if rewritten to overcome the 112 rejections above. The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Kim (US 2018/0277543), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim: Regarding Claim 1 (from which claims 2-6 depend), a first channel layer disposed on the gate electrode layer, wherein the first channel layer includes a two-dimensional semiconductor material… Regarding Claim 7 (from which claims 8-12 depend), forming a first channel layer disposed on one gate electrode layer of the gate electrode layers, wherein the first channel layer comprises a two-dimensional semiconductor material… Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim (US 2018/0277543) discloses (Figs. 3A-3B) a substrate 100 with two source/drain regions SD1/SD2, gate region GE, a channel CH1 on and inside GE, SD1/SD2 coplanar with GE. Kim does not disclose two air spacers below the channel layer and between the gate region and source and drain. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GUSTAVO G RAMALLO/Examiner, Art Unit 2812
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Prosecution Timeline

Jul 19, 2024
Application Filed
Aug 25, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751007
MEMORY DEVICE WITH REDUCED RESISTANCE
4y 2m to grant Granted Sep 29, 2026
Patent 12745396
VERTICAL SEMICONDUCTOR DEVICE
3y 7m to grant Granted Sep 22, 2026
Patent 12745630
ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
3y 1m to grant Granted Sep 22, 2026
Patent 12740058
NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
3y 4m to grant Granted Sep 15, 2026
Patent 12740064
LOW-COST MASK PUNCH FLOW
3y 4m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
98%
With Interview (+2.4%)
2y 3m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 584 resolved cases by this examiner. Grant probability derived from career allowance rate.

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