Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitations "the conductive material" and “the recessed regions” in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-9, and 14-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tu (US 7,666,737).
Regarding claim 1, Tu discloses a method of manufacturing a capacitor structure, comprising:
forming an alternating dielectric stack (21) comprising first dielectric layers (22) and second dielectric layers (24) on a substrate (14/10) [Fig. 1B];
forming a trench (26) through the alternating stack of first dielectric layers and second dielectric layers [Fig. 1C];
etching the first dielectric layers (22) from the trench to form notches (27) between the second dielectric layers (24) [Figs. 1D];
forming a bottom electrode layer (28) covering the first dielectric layers and the second dielectric layers [Fig. 1E];
forming a third dielectric layer (30) over the bottom electrode layer [Fig. 1F]; and
forming a top electrode layer (32) over the third dielectric layer [Fig. 1F].
Regarding claim 2, Tu discloses:
forming a via structure (16) in an interconnect structure within the substrate [Fig. 1A],
wherein forming the trench (26) further comprises exposing the via structure [Fig. 1C], and
wherein forming the bottom electrode layer (28) further comprises conductively coupling the bottom electrode layer to the via within the interconnect structure [Fig. 1E]..
Regarding claim 4, Tu discloses:
forming the top electrode layer (32) such that the top electrode layer comprises portions extending into the notches (27) such that a width of a bottom surface of the top electrode layer (32) is greater than a width of the trench (26) [Figs.1C and 1F].
Regarding claim 6, Tu discloses a method of manufacturing a capacitor structure, the method comprising:
forming an alternating dielectric stack (21) comprising first dielectric layers (22) and second dielectric layers (24) [Fig. 1B];
forming a trench (26) through the alternating stack of first dielectric layers and second dielectric layers [Fig. 1C];
selectively etching the first dielectric layers (22) from the trench to create recessed regions (27) between the second dielectric layers (27) [Fig. 1D];
depositing a conductive material (28) within the recessed regions to form a bottom electrode layer (28) [Fig. 1E];
conformally depositing a third dielectric layer (30) over the conductive material and the second dielectric layers [Fig 1F]; and
forming a top electrode layer (32) over the third dielectric layer [Fig. 1F].
Regarding claim 7, Tu discloses forming a via structure (16) in an interconnect structure under the alternating dielectric stack (21) [Fig. 1B].
Regarding claim 8, Tu discloses wherein forming the trench (26) further comprises exposing the via structure (16) [Fig. 1C].
Regarding claim 9, Tu discloses wherein depositing the conductive material (28) within the recessed regions (27) to form the bottom electrode layer (28) comprises conductively coupling the bottom electrode layer (28) to the via structure (16) within the interconnect structure [Fig. 1E].
Regarding claim 14, Tu discloses a method of manufacturing a capacitor structure, the method comprising:
forming an alternating dielectric stack (21) comprising first dielectric layers (22) and second dielectric layers (24) on a substrate (14/10) [Fig. 1B];
forming a trench (26) through the alternating stack of first dielectric layers and second dielectric layers [Fig. 1C];
removing the first dielectric layers (22) from the trench to form cavities (27) between the second dielectric layers (24) [Fig. 1D];
depositing a bottom electrode layer (28) such that it covers the exposed surfaces of the second dielectric layers and extends into the cavities [Fig. 1E];
depositing a third dielectric layer (30) over the bottom electrode layer and within the cavities [Fig. 1F]; and
depositing a top electrode layer (32) over the third dielectric layer [Fig. 1F].
Regarding claim 15, Tu discloses forming a via structure (16) in an interconnect structure within the substrate [Fig. 1A].
Regarding claim 16, Tu discloses wherein forming the trench (26) further comprises exposing the via structure (16) [Fig. 1C].
Regarding claim 17, Tu discloses wherein depositing the conductive material (28) within the recessed regions (cavities 27) to form the bottom electrode layer (28) comprises conductively coupling the bottom electrode layer (32) to the via structure (16) within the interconnect structure [Fig. 1E].
Claims 1, 3-4, 6, 10, 14, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu (US 5,910,667).
Regarding claim 1, Hsu discloses a method of manufacturing a capacitor structure, comprising:
forming an alternating dielectric stack (511) comprising first dielectric layers (59) and second dielectric layers (510) on a substrate (50) [Fig. 5B];
forming a trench (55) through the alternating stack of first dielectric layers and second dielectric layers [Fig. 5C];
etching the first dielectric layers (59) from the trench to form notches (514) between the second dielectric layers (510) [Figs. 5D];
forming a bottom electrode layer (515) covering the first dielectric layers and the second dielectric layers [Fig. 5E];
forming a third dielectric layer (516) over the bottom electrode layer [Fig. 5F]; and
forming a top electrode layer (517) over the third dielectric layer [Fig. 5F].
Regarding claim 3, Hsu discloses:
forming a fourth dielectric layer (519) over the top electrode layer (517) such that a bottommost portion of the fourth dielectric layer is lower than a bottommost surface of the second dielectric layers (510) [Fig. 5G].
Regarding claim 4, Hsu discloses:
forming the top electrode layer (517) such that the top electrode layer comprises portions extending into the notches (514) such that a width of a bottom surface of the top electrode layer (517) is greater than a width of the trench (55) [Figs.5C and 5F].
Regarding claim 6, Tu discloses a method of manufacturing a capacitor structure, the method comprising:
forming an alternating dielectric stack (511) comprising first dielectric layers (59) and second dielectric layers (510) [Fig. 5B];
forming a trench (55) through the alternating stack of first dielectric layers and second dielectric layers [Fig. 5C];
selectively etching the first dielectric layers (59) from the trench to create recessed regions (514) between the second dielectric layers (510) [Fig. 5D];
depositing a conductive material (515) within the recessed regions to form a bottom electrode layer (515) [Fig. 5E];
conformally depositing a third dielectric layer (516) over the conductive material and the second dielectric layers [Fig 5F]; and
forming a top electrode layer (517) over the third dielectric layer [Fig. 5F].
Regarding claim 10, Hsu discloses:
forming a fourth dielectric layer (519) over the top electrode layer (517) such that a bottommost portion of the fourth dielectric layer is lower than a bottommost surface of the second dielectric layers (510) [Fig. 5G].
Regarding claim 14, Hsu discloses a method of manufacturing a capacitor structure, the method comprising:
forming an alternating dielectric stack (511) comprising first dielectric layers (59) and second dielectric layers (510) on a substrate (50) [Fig. 5B];
forming a trench (55) through the alternating stack of first dielectric layers and second dielectric layers [Fig. 5C];
removing the first dielectric layers (59) from the trench to form cavities (514) between the second dielectric layers (510) [Fig. 5D];
depositing a bottom electrode layer (515) such that it covers the exposed surfaces of the second dielectric layers and extends into the cavities [Fig. 5E];
depositing a third dielectric layer (516) over the bottom electrode layer and within the cavities [Fig. 5F]; and
depositing a top electrode layer (517) over the third dielectric layer [Fig. 5F].
Regarding claim 18, Hsu discloses:
forming a fourth dielectric layer (519) over the top electrode layer (517) such that a bottommost portion of the fourth dielectric layer is lower than a bottommost surface of the second dielectric layers (510) [Fig. 5G].
Allowable Subject Matter
Claims 5, 11-13, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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