DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the, “the second electrical insulator layer has a first depth measured from the top surface of the semiconductor substrate to a bottom surface of the second electrical insulator layer below the top surface of the semiconductor substrate, the third electrical insulator layer has a second depth measured from the top surface of the semiconductor substrate to a bottom surface of the third electrical insulator layer below the top surface of the semiconductor substrate, and the first depth is at least two times the second depth,” of claim 18 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation, “the third electrical insulator layer has a second depth measured from the top surface of the semiconductor substrate to a bottom surface of the third electrical insulator layer below the top surface of the semiconductor substrate,” in lines 5-7 of the claim. The meets and bounds of this limitation are unclear, as the measurement locations are unclear for defining the depth. The bottom surface of the third electrical insulator layer is slanted with respect to the vertical direction, and therefore, a depth measured to this surface could result in a number of different depths based on a chosen location along this slanted surface. Claim 18 also recites the limitation, “the second electrical insulator layer has a first depth measured from the top surface of the semiconductor substrate to a bottom surface of the second electrical insulator layer,” in lines 2-4 of the claim. The meets and bounds of this limitation are unclear, as the measurement locations are unclear for defining the depth. There are three bottom surfaces of the second electrical insulator layer with two of these bottom surface being slanted bottom surfaces; a depth measured to a bottom surface could mean a number of different depths. Claim 18 also recites the limitation, “and the first depth is at least two times the second depth,” in line 8 of the claim. The meets and bounds of this limitation are unclear, as it is unclear whether the first depth is at least two times larger than the second depth or is at least two times smaller than the second depth. The specification fails to provide further clarity, as the relevant figures 11-13 reveal depths as measured from a top surface of an etch stop layer 106 and relevant paragraphs 46-56, 69-70 compare height-to-width aspect ratios of features as opposed to comparing depths of features. For the purpose of this office action, the above limitation of line 8 of claim 18 is interpreted to have the following meaning: and the first depth is at least two times larger than the second depth.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 11, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US PGPub 20130181286 A1; hereinafter referred to as "Zhang”) in view of Huang et al. (US 6235606 B1; hereinafter referred to as "Huang”).
Re claim 1: Zhang teaches a semiconductor arrangement, comprising: a first isolation structure (FIG. 1A: el. 185; para. 23, 44) disposed within a semiconductor substrate (FIG. 1A: el. 105; para. 13), the first isolation structure comprising: a first electrical insulator layer (FIG. 1A: el. 185); and a doped region (FIG. 1A: el. (134, 150, 170); para. 19, 46-47) laterally adjacent and underlying the first isolation structure (FIG. 1A: el. (134, 150, 170), 185), wherein: a first portion of the doped region has a first concentration of dopants (FIG. 1A: el. 134), a second portion of the doped region has a second concentration of dopants (FIG. 1A: el. 150) different than the first concentration of dopants (FIG. 1A: el. 150, 134; para. 19, 46, 14), and a first portion of a sidewall of the first isolation structure is in contact with the first portion of the doped region and a second portion of the sidewall of the first isolation structure below the first portion is in contact with the second portion of the doped region (FIG. 1A: el. 134, 150, 185|a portion of the sidewall of first isolation structure 185 is in contact with the first portion 134 of the doped region and a second lower portion of the sidewall of first isolation structure 185 is in contact with the second portion 150 of the doped region). Zhang fails to teach a second electrical insulator layer, wherein the second electrical insulator layer is separated from the semiconductor substrate by the first electrical insulator layer.
In a similar field of endeavor, Huang teaches a shallow trench isolation structure adjacent to a doped region (FIG. 2H: el. (206, 208, 210), 222; col. 3: line 9-34, col. 3: line 59-col. 4: line 2). Huang teaches a semiconductor arrangement, comprising: a first isolation structure disposed within a semiconductor substrate (FIG. 2H: el. (206, 208, 210), 200; col. 3: line 9-34), the first isolation structure comprising: a first electrical insulator layer (FIG. 2H: el. 206); and a second electrical insulator layer (FIG. 2H: el. 208), wherein the second electrical insulator layer is separated from the semiconductor substrate by the first electrical insulator layer (FIG. 2H: el. 208, 200, 206). Huang also teaches a benefit of the isolation structure with multiple insulator layers is improved isolation ability, reduced leakage, and increased reliability of contacts integrated with an adjacent doped region (col. 4: line 23-43, col. 1: line 17-29).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Zhang and Huang, to enable using second electrical insulator layer of Huang in the semiconductor arrangement of Zhang, for the benefit of reduced leakage, improved isolation ability of the isolation structure, and increased reliability of contacts integrated with an adjacent doped region.
Re claim 4: The combination of Zhang and Huang teaches the semiconductor arrangement of claim 1, wherein the second portion of the doped region contacts a bottom surface of the first isolation structure (Zhang – FIG. 1A: el. 150, 185).
Re claim 5: The combination of Zhang and Huang teaches the semiconductor arrangement of claim 1, wherein the first electrical insulator layer has a first density and the second electrical insulator layer has a second density different than the first density (Huang – FIG. 2H: el. 206, 208; col. 3: line 13-29, line 39-47, col. 4: line 24-43| Huang teaches forming the first electrical insulator layer 206 (and a third electrical insulator layer 210) of an oxide material and forming the second electrical insulator layer 208 of a different composition, namely silicon rich-oxide, which has a different etching rate because of the composition/stoichiometry difference and would also result in a different density).
Re claim 6: The combination of Zhang and Huang teaches the semiconductor arrangement of claim 1, wherein: the first isolation structure comprises a third electrical insulator layer (Huang - FIG. 2H: el. 210; col. 3: line 39-47), and the third electrical insulator layer is separated from the semiconductor substrate by the second electrical insulator layer (Huang - FIG. 2H: el. 210, 200, 208).
Re claim 11: The combination of Zhang and Huang teaches the semiconductor arrangement of claim 1, comprising: a source/drain region (Huang – FIG. 2H: el. 222; col. 3: line 59-col. 4: line 2) (Zhang – 134; para. 44, 60), wherein the first electrical insulator layer is between the source/drain region and the second electrical insulator layer (Huang – FIG. 2H: el. 206, 222, 208).
Re claim 16: Zhang teaches a semiconductor arrangement, comprising: an isolation structure (FIG. 1A: el. 185; para. 23, 44) disposed in a semiconductor substrate (FIG. 1A: el. 105; para. 13), the isolation structure comprising: a first electrical insulator layer (FIG. 1A: el. 185). Zhang fails to teach a second electrical insulator layer over the first electrical insulator layer, wherein: a first sidewall of the first electrical insulator layer faces the second electrical insulator layer and a second sidewall of the first electrical insulator layer faces away from the second electrical insulator layer, in a first plane extending substantially parallel to a top surface of the semiconductor substrate, the first electrical insulator layer has a first width measured from the first sidewall to the second sidewall, in a second plane extending substantially parallel to the top surface of the semiconductor substrate, the first electrical insulator layer has a second width measured from the first sidewall to the second sidewall, the second plane is closer to the top surface of the semiconductor substrate than the first plane, and the second width is less than the first width.
In a similar field of endeavor, Huang teaches a shallow trench isolation structure adjacent to a doped region (FIG. 2H: el. (206, 208, 210), 222; col. 3: line 9-34, col. 3: line 59-col. 4: line 2). Huang teaches an isolation structure comprising: a first electrical insulator layer (FIG. 2H: el. 206; col. 3: line 9-34); and a second electrical insulator layer (FIG. 2H: el. 208; col. 3: line 9-34) over the first electrical insulator layer (FIG. 2H), wherein: a first sidewall of the first electrical insulator layer faces the second electrical insulator layer and a second sidewall of the first electrical insulator layer faces away from the second electrical insulator layer (FIG. 2H: el. 206, 208), in a first plane extending substantially parallel to a top surface of the semiconductor substrate, the first electrical insulator layer has a first width measured from the first sidewall to the second sidewall, in a second plane extending substantially parallel to the top surface of the semiconductor substrate, the first electrical insulator layer has a second width measured from the first sidewall to the second sidewall, the second plane is closer to the top surface of the semiconductor substrate than the first plane, and the second width is less than the first width (annotated FIG. 2H: el. 2nd width, 1st width|1st and 2nd planes and 1st and 2nd widths of first electrical insulator layer 206 labelled in annotated FIG. 2H, provided below; 2nd width is less than the 1st width). Huang also teaches a benefit of the isolation structure with multiple insulator layers is improved isolation ability, reduced leakage, and increased reliability of contacts integrated with an adjacent doped region (col. 4: line 23-43, col. 1: line 17-29).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Zhang and Huang, to enable using second electrical insulator layer of Huang in the semiconductor arrangement of Zhang, for the benefit of reduced leakage, improved isolation ability of the isolation structure, and increased reliability of contacts integrated with an adjacent doped region.
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Re claim 17: The combination of Zhang and Huang teaches the semiconductor arrangement of claim 16, wherein the isolation structure comprises a third electrical insulator layer (Huang – FIG. 2H: el. 210; col. 3: line 13-34) over the second electrical insulator layer (Huang – FIG. 2H: el. 210, 208).
Re claim 18: The combination of Zhang and Huang teaches the semiconductor arrangement of claim 17, wherein: the second electrical insulator layer has a first depth measured from the top surface of the semiconductor substrate to a bottom surface of the second electrical insulator layer below the top surface of the semiconductor substrate (Huang - annotated FIG. 2H: el. 1st depth|1st depth between top surface of substrate and slanted bottom surface of second electrical insulator layer labelled in annotated FIG. 2H, provided below), the third electrical insulator layer has a second depth measured from the top surface of the semiconductor substrate to a bottom surface of the third electrical insulator layer below the top surface of the semiconductor substrate, and the first depth is at least two times larger than the second depth (Huang - annotated FIG. 2H: el. 2nd depth|2nd depth between top surface of substrate and slanted bottom surface of third electrical insulator layer labelled in annotated FIG. 2H, provided below; 1st depth is at least two times larger than the 2nd depth).
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Re claim 19: The combination of Zhang and Huang teaches the semiconductor arrangement of claim 16, wherein: the first electrical insulator layer is a first oxide layer, and the second electrical insulator layer is a second oxide layer (Huang – FIG. 2H: el. 206, 208; col. 3: line 13-29|first electrical insulator 206 formed of oxide layer and second electrical insulator layer formed of silicon-rich oxide).
Re claim 20: The combination of Zhang and Huang teaches the semiconductor arrangement of claim 16, comprising: a doped region (Zhang- FIG. 1A: el. (134, 150, 170); para. 19, 46-47) surrounding at least a first sidewall, a second sidewall, and a bottom surface of the isolation structure (Zhang - FIG. 1A: el. 185, (134, 150, 170).
Claims 2-3 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Huang as applied to claim 1 above, and further in view of Cortes et al. (“Punch-through Effects in RF Bulk LDMOS Transistors,” pg. 344-347; hereinafter referred to as “Cortes”).
Re claim 2: The combination of Zhang and Huang teaches the semiconductor arrangement of claim 1, wherein a third portion of the doped region (Zhang - FIG. 1A: el. 170; para. 47) has a third concentration of dopants different than the first concentration of dopants and may be different than the second concentration of dopants (Zhang - FIG. 1A: el. 170, 134, 150; para. 14, 19, 46-47). The combination of Zhang and Huang fails to specifically disclose a difference in concentration of dopants between the third and second portions of the doped region.
In a similar field of endeavor, Cortes teaches a laterally diffused metal oxide semiconductor (LDMOS) with three doped portions (pg. 344; FIG. 1) in similar form to the LDMOS structure of Zhang. Cortes teaches a semiconductor arrangement, wherein a third portion of the doped region has a third concentration of dopants different than the second concentration of dopants (pg. 346: FIG. 6; pg. 347: para. 1-2; pg. 345: Table 1|third doped portion (body region) has a different concentration of dopants than the second doped portion (drift region) to improve the breakdown voltage). Zhang teaches a benefit of the third portion having a different and higher concentration of dopants than the second region, is an improvement in the breakdown punch-through voltage of the LDMOS semiconductor arrangement (pg. 347: para. 1-2; pg. 346: FIG. 6).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Zhang and Huang with the teachings of Cortes, to enable using the difference in concentration of the third portion of Cortes in the semiconductor arrangement of the combination of Zhang and Huang, for the benefit of an improvement in the punch-through breakdown voltage of the semiconductor arrangement.
Re claim 3: The combination of Zhang, Huang and Cortes teaches the semiconductor arrangement of claim 2, wherein the third portion of the doped region (Zhang – FIG. 1A: el. 170) is spaced apart from the first isolation structure by the second portion of the doped region (Zhang – FIG. 1A: el. 170, 185, 150).
Re claim 7: The combination of Zhang and Huang teaches the semiconductor arrangement of claim 1, wherein: a third portion (Zhang - FIG. 1A: el. 170; para. 47) of the doped region may have a third concentration of dopants different than the second concentration of dopants (Zhang - FIG. 1A: el. 170, 134, 150; para. 14, 19, 46-47), the semiconductor arrangement comprises a second isolation structure (Zhang – FIG. 1A: el. 180; para. 16), the third portion of the doped region is spaced apart from a bottom surface of the first isolation structure by the second portion of the doped region (Zhang – FIG. 1A: el. 170, 185, 150), and the third portion of the doped region contacts a bottom surface of the second isolation structure (Zhang – FIG. 1A: el. 170, 180). The combination of Zhang and Huang fails to specifically disclose a difference in concentration of dopants between the third and second portions of the doped region.
In a similar field of endeavor, Cortes teaches a laterally diffused metal oxide semiconductor (LDMOS) with three doped portions (pg. 344; FIG. 1) in similar form to the LDMOS structure of Zhang. Cortes teaches a semiconductor arrangement, wherein a third portion of the doped region has a third concentration of dopants different than the second concentration of dopants (pg. 346: FIG. 6; pg. 347: para. 1-2; pg. 345: Table 1|third doped portion (body region) has a different concentration of dopants than the second doped portion (drift region) to improve the breakdown voltage). Zhang teaches a benefit of the third portion having a different and higher concentration of dopants than the second region, is an improvement in the breakdown punch-through voltage of the LDMOS semiconductor arrangement (pg. 347: para. 1-2; pg. 346: FIG. 6).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Zhang and Huang with the teachings of Cortes, to enable using the difference in concentration of the third portion of Cortes in the semiconductor arrangement of the combination of Zhang and Huang, for the benefit of an improvement in the punch-through breakdown voltage of the semiconductor arrangement.
Re claim 8: The combination of Zhang, Huang and Cortes teaches the semiconductor arrangement of claim 7, wherein the second portion of the doped region contacts the bottom surface of the second isolation structure (Zhang – FIG. 1A: el. 150, 180).
Re claim 9: The combination of Zhang, Huang and Cortes teaches the semiconductor arrangement of claim 7, wherein the second portion of the doped region contacts the bottom surface of the first isolation structure (Zhang – FIG. 1A: el. 170, 185).
Re claim 10: The combination of Zhang, Huang and Cortes teaches the semiconductor arrangement of claim 7, wherein the second portion of the doped region contacts the bottom surface of the first isolation structure (Zhang – FIG. 1A: el. 150, 185) and the bottom surface of the second isolation structure (Zhang – FIG. 1A: el. 150, 180).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Huang and Cortes.
Re claim 12: Zhang teaches a semiconductor arrangement, comprising: a first isolation structure (FIG. 1A: el. 185; para. 23, 44) disposed within a semiconductor substrate (FIG. 1A: el. 105; para. 13), the first isolation structure comprising: a first electrical insulator layer (FIG. 1A: el. 185); a second isolation structure (FIG. 1A: el. 180; para. 16); and a doped region (FIG. 1A: el. (134, 150, 170); para. 19, 46-47) between the first isolation structure and the second isolation structure (FIG. 1A: el. (134, 150, 170), 185, 180), wherein: a first portion (FIG. 1A: el. 150) of the doped region has a first concentration of dopants (FIG. 1A: el. 150; para. 46), a second portion (FIG. 1A: el. 170) of the doped region may have a second concentration of dopants different than the first concentration of dopants, the second portion (FIG. 1A: el. 170) of the doped region is spaced apart from a bottom surface of the first isolation structure by the first portion of the doped region (FIG. 1A: el. 170, 185, 150), and the second portion of the doped region is in contact with a bottom surface of the second isolation structure (FIG. 1A: el. 170, 180). Zhang fails to disclose a second electrical insulator layer and fails to specifically disclose a second portion of the doped region has a second concentration of dopants different than the first concentration of dopants.
In a similar field of endeavor, Huang teaches a shallow trench isolation structure adjacent to a doped region (FIG. 2H: el. (206, 208, 210), 222; col. 3: line 9-34, col. 3: line 59-col. 4: line 2). Huang teaches a semiconductor arrangement, comprising: a first isolation structure disposed within a semiconductor substrate (FIG. 2H: el. (206, 208, 210), 200; col. 3: line 9-34), the first isolation structure comprising: a first electrical insulator layer (FIG. 2H: el. 206); and a second electrical insulator layer (FIG. 2H: el. 208. Huang also teaches a benefit of the isolation structure with multiple insulator layers is improved isolation ability, reduced leakage, and increased reliability of contacts integrated with an adjacent doped region (col. 4: line 23-43, col. 1: line 17-29).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Zhang and Huang, to enable using second electrical insulator layer of Huang in the semiconductor arrangement of Zhang, for the benefit of reduced leakage, improved isolation ability of the isolation structure, and increased reliability of contacts integrated with an adjacent doped region.
The combination of Zhang and Huang fails to specifically disclose a second portion of the doped region has a second concentration of dopants different than the first concentration of dopants.
In a similar field of endeavor, Cortes teaches a laterally diffused metal oxide semiconductor (LDMOS) with three doped portions (pg. 344; FIG. 1) in similar form to the LDMOS structure of Zhang. Cortes teaches a semiconductor arrangement, wherein a second portion of the doped region has a second concentration of dopants different than the first concentration of dopants (pg. 346: FIG. 6; pg. 347: para. 1-2; pg. 345: Table 1|second doped portion (body region) has a different concentration of dopants than the first doped portion (drift region) to improve the breakdown voltage). Zhang teaches a benefit of the second portion having a different and higher concentration of dopants than the first region, is an improvement in the breakdown punch-through voltage of the LDMOS semiconductor arrangement (pg. 347: para. 1-2; pg. 346: FIG. 6).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Zhang and Huang with the teachings of Cortes, to enable using the difference in concentration of the second portion of Cortes in the semiconductor arrangement of the combination of Zhang and Huang, for the benefit of an improvement in the punch-through breakdown voltage of the semiconductor arrangement.
Re claim 13: The combination of Zhang, Huang and Cortes teaches the semiconductor arrangement of claim 12, wherein the first portion (Zhang- FIG. 1A: el. 150) of the doped region is in contact with the bottom surface of the first isolation structure and the bottom surface of the second isolation structure (Zhang – FIG. 1A: el. 150, 185, 180).
Re claim 14: The combination of Zhang, Huang and Cortes teaches the semiconductor arrangement of claim 12, wherein a third portion (Zhang- FIG. 1A: el. 134; para. 19) of the doped region is over the first portion (Zhang- FIG. 1A: el. 150) of the doped region and has a third concentration of dopants different than the first concentration of dopants (Zhang- FIG. 1A: el. 150, 134; para. 14, 19, 46).
Re claim 15: The combination of Zhang, Huang and Cortes teaches the semiconductor arrangement of claim 14, wherein: the third portion of the doped region is in contact with a first portion of a sidewall of the first isolation structure (Zhang- FIG. 1A: el. 134, 185), and the first portion of the doped region is in contact with a second portion of the sidewall of the first isolation structure (Zhang- FIG. 1A: el. 150, 185).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. 12094756 (Chen et al.; hereinafter referred to as ’756). Although the claims at issue are not identical, they are not patentably distinct from each other. Claim 17 of ‘756 discloses the limitations of claim 1 of the instant application and also discloses additional limitations.
Instant Application
US 12094756 B2
Claim 1:
A semiconductor arrangement, comprising: a first isolation structure disposed within a semiconductor substrate, the first isolation structure comprising:
a first electrical insulator layer;
and a second electrical insulator layer, wherein the second electrical insulator layer is separated from the semiconductor substrate by the first electrical insulator layer;
and a doped region laterally adjacent and underlying the first isolation structure, wherein: a first portion of the doped region has a first concentration of dopants, a second portion of the doped region has a second concentration of dopants different than the first concentration of dopants,
and a first portion of a sidewall of the first isolation structure is in contact with the first portion of the doped region and a second portion of the sidewall of the first isolation structure below the first portion is in contact with the second portion of the doped region.
Claim 17:
A semiconductor arrangement, comprising: an isolation structure disposed within a semiconductor substrate, the isolation structure comprising:
a first electrical insulator layer having a first density, wherein the first electrical insulator layer has a first depth measured from a top surface of the semiconductor substrate to a bottommost surface of the first electrical insulator layer;
and a second electrical insulator layer having a second density different than the first density, wherein: the second electrical insulator layer is laterally separated from the semiconductor substrate by the first electrical insulator layer,
the second electrical insulator layer has a second depth measured from the top surface of the semiconductor substrate to a bottommost surface of the second electrical insulator layer, and the first depth is at least two times the second depth;
and a doped region laterally adjacent and underlying the isolation structure, wherein: a first portion of the doped region has a first concentration of dopants, a second portion of the doped region has a second concentration of dopants different than the first concentration of dopants,
and a first portion of a sidewall of the isolation structure is in contact with the first portion of the doped region and a second portion of the sidewall of the isolation structure below the first portion is in contact with the second portion of the doped region.
Claim 6 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of U.S. Patent No. 12094756 (Chen et al.; hereinafter referred to as ’756). Although the claims at issue are not identical, they are not patentably distinct from each other. Claim 18 of ‘756 discloses the limitations of claim 6 of the instant application and also discloses additional limitations.
Instant Application
US 12094756 B2
Claim 1: compared in above table
Claim 6:
The semiconductor arrangement of claim 1, wherein: the first isolation structure comprises a third electrical insulator layer,
and the third electrical insulator layer is separated from the semiconductor substrate by the second electrical insulator layer.
Claim 17: compared in above table
Claim 18:
The semiconductor arrangement of claim 17, comprising a third electrical insulator layer,
wherein the third electrical insulator layer is laterally separated from the semiconductor substrate by the second electrical insulator layer.
Claim 11 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 19 of U.S. Patent No. 12094756 (Chen et al.; hereinafter referred to as ’756). Although the claims at issue are not identical, they are not patentably distinct from each other. Claim 19 of ‘756 discloses the limitations of claim 11 of the instant application and also discloses additional limitations.
Instant Application
US 12094756 B2
Claim 1: compared in above table
Claim 11:
The semiconductor arrangement of claim 1, comprising: a source/drain region, wherein the first electrical insulator layer is between the source/drain region and the second electrical insulator layer.
Claim 17: compared in above table
Claim 19:
The semiconductor arrangement of claim 17, comprising a source/drain region, wherein the first electrically insulator layer is between the source/drain region and the second electrical insulator layer.
Claims 16 and 17 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12094756 (Chen et al.; hereinafter referred to as ’756). Although the claims at issue are not identical, they are not patentably distinct from each other. Claim 1 of ‘756 discloses the limitations of claim 16 and 17 of the instant application and also discloses additional limitations.
Instant Application
US 12094756 B2
Claim 16:
A semiconductor arrangement, comprising: an isolation structure disposed in a semiconductor substrate, the isolation structure comprising:
a first electrical insulator layer;
and a second electrical insulator layer over the first electrical insulator layer,
wherein: a first sidewall of the first electrical insulator layer faces the second electrical insulator layer and a second sidewall of the first electrical insulator layer faces away from the second electrical insulator layer,
in a first plane extending substantially parallel to a top surface of the semiconductor substrate, the first electrical insulator layer has a first width measured from the first sidewall to the second sidewall, in a second plane extending substantially parallel to the top surface of the semiconductor substrate, the first electrical insulator layer has a second width measured from the first sidewall to the second sidewall,
the second plane is closer to the top surface of the semiconductor substrate than the first plane, and the second width is less than the first width.
Claim 17:
The semiconductor arrangement of claim 16, wherein the isolation structure comprises a third electrical insulator layer over the second electrical insulator layer.
Claim 1:
A semiconductor arrangement, comprising: an isolation structure comprising:
a first electrical insulator layer in a trench in a semiconductor substrate;
a second electrical insulator layer in the trench and over the first electrical insulator layer,
wherein: a first sidewall of the first electrical insulator layer faces the second electrical insulator layer and a second sidewall of the first electrical insulator layer faces away from the second electrical insulator layer,
in a first plane extending substantially parallel to a top surface of the semiconductor substrate, the first electrical insulator layer has a first width measured from the first sidewall to the second sidewall, in a second plane extending substantially parallel to the top surface of the semiconductor substrate, the first electrical insulator layer has a second width measured from the first sidewall to the second sidewall,
the second plane is closer to the top surface of the semiconductor substrate than the first plane, and the second width is less than the first width;
and a third electrical insulator layer in the trench and over the second electrical insulator layer, wherein the third electrical insulator layer fills a remainder of the trench not occupied by the first electrical insulator layer and the second electrical insulator layer.
Claim 19 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12094756 (Chen et al.; hereinafter referred to as ’756). Although the claims at issue are not identical, they are not patentably distinct from each other. Claim 8 of ‘756 discloses the limitations of claim 19 of the instant application and also discloses additional limitations.
Instant Application
US 12094756 B2
Claim 16: compared in above table
Claim 19:
The semiconductor arrangement of claim 16, wherein: the first electrical insulator layer is a first oxide layer, and the second electrical insulator layer is a second oxide layer.
Claim 1: compared in above table
Claim 8:
The semiconductor arrangement of claim 1, wherein: the first electrical insulator layer is a first oxide layer, and the second electrical insulator layer is a second oxide layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art made of record and not relied upon discloses multilayer isolation structures.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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