DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, Species I, (claims 1-7, 9-10, 21-30) in the reply filed on 08/26/2026 is acknowledged.
Claim 8 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/10/11.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6, 9, 28-30 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 28 defines “a first part” and claim 29 defines “a second part”, claim 30 defines “an additional part” are not marked or labeled and not clear what parts it is referring to. For examination purpose, residue portion of 84’s will be examined as a first part and a second part.
Claim 29 defines “a third top surface” is not marked or labeled and not clear what parts it is referring to. Appropriate markings/explanation is required.
Claim 6 define “after a semiconductor substrate of the substrate” is not clear what it means. In view of the specification it will be examined as a semiconductor layer of the substrate.
Claim 9 defines “into a semiconductor substrate of the substrate” is not clear what it means. In view of the specification it will be examined into a semiconductor layer of the substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being obvious over Liang et al (US 2020/0135599 A1) in view of Chang et al. (20180033695 A1)
Regarding claim 1: Liang teaches in Fig.s 13-15 about a method comprising:
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performing a first plurality of laser grooving processes 131 on a scribe line 502 (Fig. 5) of a substrate 500 to form a first combined groove (left 1301);
performing a second plurality of laser grooving processes 131 on the scribe line of the substrate to form a second combined groove (right 1301);
performing a first sawing process 140 on the scribe line of the substrate, wherein the first sawing process is performed in a part of the scribe line between the first combined groove and the second combined groove (Fig. 14); and
performing a second sawing process 150 to saw through the substrate in the scribe line, wherein the second sawing process separates a first device die (under 501A of Fig. 13) and a second device die (under 502B of Fig. 13) on opposing sides of the scribe line from each other (Fig. 15).
Liang does not explicitly show a first plurality of laser grooving processes to form a first combined groove and a second plurality of laser grooving processes to form a second combined groove.
Chang teaches in Fig. 3-4 about a plurality of laser grooving processes 204A-204I to form a first combined groove 206 (Fig. 4).
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Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to use Chang’s method in Liang’s method of forming the left groove 1301 using a first plurality of laser grooving processes to form a first combined groove and forming the right groove 1301 using a second plurality of laser grooving processes to form a second combined groove and thereby having the combined grove/kerf with a specific profile and/or dimensions in order to reduce manufacturing defects resulting from singulation (Chang, [0027]).
Regarding claim 2: Chang teaches in Fig. 3 wherein the first plurality of laser grooving processes comprise: a first grooving process 204A along a first path in the scribe line 202; and
a second grooving process 204C along a second path in the scribe line, wherein the second path partially overlaps the first path.
Regarding claim 3: Chang teaches in Fig. 3 wherein the first plurality of laser grooving processes further comprise: a third grooving process 204E along a third path in the scribe line, wherein the third path partially overlaps the second path.
Regarding claim 4: Chang teaches in Fig. 3 wherein the first combined groove 206 is wider than a single groove any 204A-204I that is generated by a single grooving process comprised in the first plurality of laser grooving processes.
Regarding claim 5: Liang teaches in Fig. 14 wherein the first sawing process generates a third groove 1302 that joins the first combined groove to the second combined groove.
Regarding claim 6: Liang teaches in Fig. 14 wherein the first sawing process is stopped after a semiconductor substrate of the substrate is exposed, and before the semiconductor substrate is sawed through.
Regarding claim 7: Liang teaches in Fig. 14 wherein the first sawing process is performed using a blade 140.
Regarding claim 9: Liang teaches in Fig. 14 wherein the first combined groove extends into a semiconductor substrate of the substrate, and at least a residue portion of semiconductor substrate (part of 500) is under the first combined groove and between two of grooves that are generated by two of the first plurality of laser grooving processes.
Regarding claim 10: Liang teaches in Fig. 15 wherein after the second sawing process, the first device die comprises a portion of the first combined groove.
Claims 21, 28-30 are rejected under 35 U.S.C. 103 as being obvious over Liang et al (US 2020/0135599 A1)
Regarding claim 21: Liang teaches in Fig. 5, 15 about a method comprising:
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separating a wafer (Fig. 5) into a plurality of device dies (501A-501D), wherein the plurality of device dies comprise a first device die 501A that comprises a semiconductor substrate 500, and wherein the semiconductor substrate comprises:
a first edge and a second edge laterally recessed from the first edge, wherein the second edge has at least a portion higher than the first edge;
a first top surface laterally between the first edge and the second edge; and
a first residue portion protruding higher than the first top surface, wherein the first residue portion is also laterally between the first edge and the second edge (as marked above).
It has been held that to be entitled to weight in method claims, the recited-structure limitations therein must affect the method in a manipulative sense, and not to amount to the mere claiming of a use of a particular structure. Ex parte Pfeiffer, 1962 C.D. 408 (1961)
Regarding claim 28: Liang teaches in Fig. 15 about a method comprising:
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forming a wafer (Fig. 5); and
separating the wafer along scribe lines of the wafer to form a device die, wherein the separating the wafer comprises a plurality of pre-grooving processes performed on one of the scribe lines of the wafer, and wherein the device die comprises:
a plurality of dielectric layers 520; and
a semiconductor substrate 500 underlying the plurality of dielectric layers, wherein the semiconductor substrate comprises:
a first top surface (as marked) underlying and contacting the plurality of dielectric layers; and
a first extension portion (as marked) laterally extending beyond a first edge of the plurality of dielectric layers, wherein the first extension portion comprises:
a second top surface (as marked) lower than the first top surface; and a first part protruding (marked as 1st residue portion) higher than the second top surface, wherein in a top view of the device die, the first part has a strip shape, with a first lengthwise direction of the first part being substantially parallel to the first edge of the plurality of dielectric layers.
Liang does not explicitly talk about wherein in a top view of the device die, the first part has a strip shape, with a first lengthwise direction of the first part being substantially parallel to the first edge of the plurality of dielectric layers.
However Liang shows in Fig. 5 a top of the device die and the first part (as marked above in Fig. 15) would be portion of 510 which is a first lengthwise direction of the first part being substantially parallel to the first edge of the plurality of dielectric layers (which would be under 501A).
Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to realize that the first part bebeing substantially parallel to the first edge of the plurality of dielectric layers when Fig. 15 would be shown in top view.
Regarding claim 29: Liang teaches in Fig. 15 wherein the semiconductor substrate further comprises a second extension portion extending laterally beyond a second edge of the plurality of dielectric layers, and wherein the second extension portion comprises:
a third top surface lower than the first top surface (as marked above); and
a second part protruding higher than the third top surface, wherein in the top view of the device die, the second part has a second lengthwise direction being perpendicular to the first lengthwise direction (as marked above).
Regarding claim 30: Liang teaches in Fig. 15 wherein the first extension portion further comprises:
an additional part C protruding higher than the second top surface, wherein in the top view of the device die, the additional part is parallel to the first part (would be similar in top view as explained in claim 28).
Claims 22-26 are rejected under 35 U.S.C. 103 as being obvious over Liang et al (US 2020/0135599 A1) in view of Lu et al (CN 1828862 A)
Regarding claim 22: Liang does not explicitly talk about wherein the wafer is separated through processes that comprise:
a first grooving process along a first path in a scribe line of the wafer; and
a second grooving process along a second path in the scribe line, wherein the second path partially overlaps the first path, wherein the first residue portion is formed between the first path and the second path.
Lu teaches in Fig. 4-5 about a first grooving process (left 54) along a first path in a scribe line of the wafer; and
a second grooving process (right 54) along a second path in the scribe line, wherein the second path partially overlaps the first path (Fig.5), wherein the first residue portion 60 is formed between the first path and the second path (For clarification, Chang teaches It should be noted that in FIG. 4, after two laser cut groove 54 is on the wafer portion 12 60 are separated. The part 60 has a portion of the IMD layer 24 and a portion of the substrate 22. In a second embodiment, the two laser cut groove 54 can be directly tightly adjacent with the other, as shown in FIG. 5. In a third embodiment, it is possible to only use a single laser beam, cutting the channel twice, while part 60 still exists. part 60 is generated after the laser cutting, in addition to other factors depending on the laser beam 46 with the other laser beam 46 and the distance between the area of the laser beam).
Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to use Lu’s method in Liang’s groove forming method thereby having the feture as claimed depending on laser factors of laser beams applied and and distance between the area of the laser beam(Lu, Fig. 4-5 description).
Regarding claim 23: Lu teaches in Fig. 4 wherein the first device die further comprises a plurality of dielectric layers (IMD 24)over the semiconductor substrate, and wherein the first residue portion further comprises a part of the plurality of dielectric layers (Fig. 4).
Regarding claim 24: Liang teaches in Fig. 15 as marked above, wherein the semiconductor substrate comprises a planar top surface joined to the second edge, and wherein a topmost end of the first residue portion is lower than the planar top surface.
Regarding claim 25: Liang teaches in Fig. 15 as marked above wherein the first top surface of the semiconductor substrate is joined to the first edge, and wherein the semiconductor substrate further comprises a second top surface joined to a bottom of the first residue portion, and wherein the first top surface and the second top surface are at different levels.
Regarding claim 26: Liang teaches in Fig. 15 as marked above wherein the first top surface of the semiconductor substrate is joined to the first edge, and is planar, and wherein the second top surface is non- planar.
Claim 27 is rejected under 35 U.S.C. 103 as being obvious over Liang et al (US 2020/0135599 A1) in view of in view of Lu et al (CN 1828862 A) and further in view of
Chen et al (US 2022/0262694 A1)
Regarding claim 27: Liang in view of Lu does not teach bonding a second device die underlying the first device die, wherein the second device die is electrically connected to the first device die; and
forming gap-fill regions on opposing sides of the second device die, wherein the gap-fill regions comprise an additional edge vertically aligned to the first edge of the semiconductor substrate.
Chen teaches in Fig. 17-18 about bonding a second device die 90 underlying the first device die 64’, wherein the second device die is electrically connected to the first device die; and
forming gap-fill regions 97 on opposing sides of the second device die, wherein the gap-fill regions comprise an additional edge vertically aligned to the first edge of the semiconductor substrate (as shown).
Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to use Chen’s method in Liang’s forming method to have the feature as claimed and warpage caused by the large package substrate is thus avoided. Due to the reduction of the warpage, it is also possible to increase the total number of the layers in the package substrate without causing yield loss (Chen, [0040).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
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