Prosecution Insights
Last updated: October 22, 2026
Application No. 18/777,807

STRAP TECHNOLOGY TO IMPROVE ESD HBM PERFORMANCE

Non-Final OA §103
Filed
Jul 19, 2024
Priority
Jul 25, 2022 — continuation of 12/132,042
Examiner
ZHU, SHENG-BAI
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
6m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
449 granted / 721 resolved
-5.7% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
57 currently pending
Career history
796
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
69.0%
+29.0% vs TC avg
§102
22.9%
-17.1% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 721 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Detailed Action Restriction/Election Applicants’ election of Invention I, without traverse, in the reply filed on 9/28/2026 is acknowledged. Claim Rejections – 35 U.S.C. 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 21-27 and 29-32 rejected under 35 U.S.C. 103 as being unpatentable over Fan (CN 114429950, machine-translation provided), in view of Huang (U.S. Patent Pub. No. 2006/0092592). Regarding Claim 21 FIG. 4 of Fan discloses an integrated circuit device, comprising: a semiconductor substrate (100); a P-well in the semiconductor substrate, wherein the P-well comprises a first P-well portion (133) and a second P-well portion (132); an N-channel grounded-gate metal-oxide-semiconductor (ggNMOS) electrostatic discharge device, wherein the ggNMOS electrostatic discharge device is disposed over the first P-well portion and comprises a plurality of MOSFET fingers (171/172); a bulk ring (103) for the ggNMOS electrostatic discharge device, wherein the bulk ring is disposed over the second P-well portion and has P-type doping; an isolation structure (124), wherein the isolation structure surrounds the ggNMOS electrostatic discharge device and is between the bulk ring and the ggNMOS electrostatic discharge device; and a strap (131) in the semiconductor substrate between the first P-well portion and the second P-well portion, wherein the strap has lighter P-type doping than the P-well or has N-type doping. Fan is silent with respect to “the strap has a plurality of slots through which the P-well has continuity between the first P-well portion and the second P-well portion”. FIG. 7C of Huang discloses a similar integrated circuit device, wherein the strap (744) has a plurality of slots through which the P-well has continuity between the first P-well portion and the second P-well portion. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fan, as taught by Huang. The ordinary artisan would have been motivated to modify Fan in the above manner for purpose of improving ESD protection circuits with adjustable trigger voltages ([0005] of Huang). Regarding Claim 22 FIG. 4 of Fan discloses the plurality of MOSFET fingers comprise a first finger (171) and a second finger (172); and the first P-well portion (133) comprises a first base region for the first finger and a second base region for the second finger, wherein there is a first resistance between the bulk ring and the first base region and a second resistance between the bulk ring and the second base region (inherent). The recitation of “the strap reduces a ratio between the first resistance and the second resistance” is only a statement of the inherent properties of the Fan product. The structure recited in Fan is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Or where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01-02. Regarding Claim 23 FIG. 4 of Fan discloses the strap is directly beneath the isolation structure (124). Regarding Claim 24 FIG. 4 of Fan discloses the strap (131) is directly beneath the bulk ring (102). Regarding Claim 25 FIG. 4 of Fan discloses the first P-well portion (133) and the second P-well portion (132) are disposed over distinct areas of the semiconductor substrate. Regarding Claim 26 FIG. 7C of Huang discloses the slots divide the strap into distinct segments. Regarding Claim 27 FIG. 4 of Fan discloses the strap (131) has N- type doping. Regarding Claim 29 FIG. 4 of Fan discloses an integrated circuit device, comprising: a semiconductor substrate (100); a buried n-layer (151) in the semiconductor substrate; a P-well in the semiconductor substrate, wherein the P-well comprises a first P-well portion (133) and a second P-well portion (132), and the P-well is over the buried n-layer; an N-channel grounded-gate metal-oxide-semiconductor (ggNMOS) electrostatic discharge device, wherein the ggNMOS electrostatic discharge device is disposed over the first P-well portion and comprises a plurality of MOSFET fingers (171/172); a bulk ring (103) for the ggNMOS electrostatic discharge device, wherein the bulk ring is disposed over the second P-well portion and has P-type doping; an isolation structure (124), wherein the isolation structure surrounds the ggNMOS electrostatic discharge device and is between the bulk ring and the ggNMOS electrostatic discharge device; and a strap (131) in the semiconductor substrate between the first P-well portion and a second P-well portion, wherein the strap is over the buried n-layer, the strap has lighter P-type doping than the P-well or has N-type doping. Fan is silent with respect to “the strap comprises a plurality of distinct segments separated by gaps”. FIG. 7C of Huang discloses a similar integrated circuit device, wherein the strap (744) comprises a plurality of distinct segments separated by gaps. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fan, as taught by Huang. The ordinary artisan would have been motivated to modify Fan in the above manner for purpose of improving ESD protection circuits with adjustable trigger voltages ([0005] of Huang). Regarding Claim 30 FIG. 4 of Fan discloses the strap extends down to the buried n-layer (151). Regarding Claim 31 FIG. 4 of Fan discloses the buried n-layer provides electrical isolation between a first portion of the semiconductor substrate that is above the buried n-layer and a second portion of the semiconductor substrate that is below the buried n-layer [0017]. Furthermore, the claimed limitation is only a functional statement. The structure recited in Fan is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Or where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01-02. Regarding Claim 32 FIG. 4 of Fan discloses the MOSFET fingers comprises source and drain regions and the strap is below a depth of the source and drain regions. Claim 28 rejected under 35 U.S.C. 103 as being unpatentable over Fan and Huang, in view of Shan (CN 102024811, machine-translation provided). Regarding Claim 28 Fan as modified by Huang discloses Claim 21. Fan as modified by Huang is silent with respect to “the strap has P- type doping”. FIG. 2 of Shan discloses a similar integrated circuit device, wherein the strap (P-well underneath p+) has P-type doping. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fan, as taught by Shan. The ordinary artisan would have been motivated to modify Fan in the above manner for purpose of providing an ESD protective circuit (Abstract of Shan). Claims 41-44 and 48 rejected under 35 U.S.C. 103 as being unpatentable over Fan, in view of Chung (EP 3021359). Regarding Claim 41 FIG. 4 of Fan discloses an integrated circuit device, comprising: a semiconductor substrate (100) comprising an active area (112-114); a P-well in the semiconductor substrate, wherein the P-well comprises a first P-well portion (133) beneath the active area and a second P-well portion (132) outside the active area; an N-channel grounded-gate metal-oxide-semiconductor (ggNMOS) electrostatic discharge device disposed over the first P-well portion and comprising a plurality of MOSFET fingers (171/172) disposed within the active area; a bulk ring (103) for the ggNMOS electrostatic discharge device, wherein the bulk ring is disposed over the second P-well portion and has P-type doping; an isolation structure (124) surrounding the active area and disposed between the active area and the bulk ring; and a strap (131) in the semiconductor substrate between the first P-well portion and the second P-well portion; wherein the strap has either N-type doping or P-type doping at a lower P-type dopant concentration than the first P-well portion and the second P-well portion; wherein the active area is rectangular and has four sides (FIG. 5). Fan is silent with respect to “the strap is selectively disposed along just two of the four sides”. FIG. 3 of Chung discloses a similar integrated circuit device, wherein the strap (204) is selectively disposed along just two of the four sides [0018]. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fan, as taught by Chung. The ordinary artisan would have been motivated to modify Fan in the above manner for purpose of preventing damage to IC caused by ESD currents ([0003] of Chung). Regarding Claim 42 FIG. 3 of Chung discloses the two sides are opposing sides and are longer than the other two sides; a length of each of the two sides is at least twice a length of each of the other two sides; and the MOSFET fingers (212) extend parallel to the two sides. Regarding Claim 43 FIG. 3 of Chung discloses the two sides are opposing sides and are longer than the other two sides; a length of each of the two sides is at least twice a length of each of the other two sides; and the MOSFET fingers extend perpendicular to the two sides. Regarding Claim 44 FIG. 3 of Chung discloses the strap comprises a first strap segment along a first one of the two sides and a second strap segment along a second one of the two sides. Modified Fan discloses each of the first and second strap segments terminates short of both ends of the corresponding side such that P-well material extends between the first P-well portion and the second P-well portion around both ends of each strap segment. Regarding Claim 48 FIG. 3 of Chung discloses the first and second strap segments collectively extend along a majority of a length of a loop around the active area. Claim 45 rejected under 35 U.S.C. 103 as being unpatentable over Fan and Huang, in view of Ker (U.S. Patent Pub. No. 2004/0070900). Regarding Claim 45 Fan as modified by Huang discloses Claim 41. Fan as modified by Huang is silent with respect to “the strap comprises a plurality of strap segments separated by periodically spaced slots along each of the two sides, each of the strap segments having a length along the corresponding side that is less than or equal to a width of the strap segment transverse to the corresponding side”. FIG. 6 of Ker discloses a similar integrated circuit device, wherein the strap (40) comprises a plurality of strap segments separated by periodically spaced slots along each of the two sides, each of the strap segments having a length along the corresponding side that is less than or equal to a width of the strap segment transverse to the corresponding side. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fan, as taught by Ker. The ordinary artisan would have been motivated to modify Fan in the above manner for purpose of coupling to ESD detection circuit ([0049] of Ker). Claim 46 rejected under 35 U.S.C. 103 as being unpatentable over Fan and Huang, in view of Chen (CN 104681542, machine-translation provided). Regarding Claim 46 Fan as modified by Huang discloses Claim 41. Fan as modified by Huang is silent with respect to “the strap has P-type doping, and a P-type dopant concentration of the strap is no greater than one hundredth of a P-type dopant concentration of the P-well”. FIG. 4 of Chen discloses a similar integrated circuit device, wherein the strap (306) is lightly P-type doped or undoped; and a P-type dopant concentration of the strap is no greater than one hundredth of a P-type dopant concentration of the P-well [0069]. Furthermore, the claimed ratio is related to ESD protection. Therefore, said ratio is considered to be a result effective variable. The claim to a specific ratio therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fan, as taught by Chen. The ordinary artisan would have been motivated to modify Fan in the above manner for purpose of improving ESD protection ([0069] of Chen). Claim 47 rejected under 35 U.S.C. 103 as being unpatentable over Fan and Huang, in view of Sun (WO 2022/073080, machine-translation provided). Regarding Claim 47 Fan as modified by Huang discloses Claim 41. Fan as modified by Huang is silent with respect to “the strap terminates above a bottom of the P-well such that a portion of the P-well extends beneath the strap between the first P-well portion and the second P-well portion”. FIG. 6 of Sun discloses a similar integrated circuit device, wherein the strap (510) terminates above a bottom of the P-well (500) such that a portion of the P-well extends beneath the strap between the first P-well portion and the second P-well portion. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fan, as taught by Sun. The ordinary artisan would have been motivated to modify Fan in the above manner for purpose of improving ESD protection capability (Abstract of Sun). Pertinent Art U.S. Patent Pub. No. 2017/0084603, 20110260254, U.S. Patent No. 9,691,752, CN 110620141, CN 113540074, CN 110600467. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jul 19, 2024
Application Filed
Sep 11, 2024
Response after Non-Final Action
Oct 14, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
68%
With Interview (+5.7%)
2y 10m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 721 resolved cases by this examiner. Grant probability derived from career allowance rate.

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