DETAILED ACTION
This Action is responsive to the Preliminary Amendment filed on 08/30/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a Non-final Office action, see 37 CFR 1.111(a). For a reply to Final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 21 is rejected on the ground of non-statutory double patenting as being anticipated by Claim 11 of U.S. Patent No. 11,292,715 (hereinafter, Lin II).
Although the claims at issue are not identical, they are not patentably distinct from each other because Lin II anticipates claims of the instant application.
Independent Claim 21 of the Instant Application is anticipated by Claim 11 of Lin II, the limitations including an integrated chip, comprising:
Instant Application
Patent No.11,292,715
a dielectric structure overlying a first substrate;
an interconnect structure overlying the substrate;
a second substrate overlying the dielectric structure and comprising a movable element;
a MEMS substrate overlying the interconnect structure, wherein the MEMS substrate comprises a moveable membrane;
a first bond structure arranged between the dielectric structure and the second substrate; and
a conductive bond ring structure sandwiched between the interconnect structure and the MEMS substrate,
a second bond structure arranged between the dielectric structure and the second substrate,
a dielectric structure sandwiched between the interconnect structure and the MEMS substrate,
wherein at least a portion of the movable element is spaced laterally between sidewalls of the second bond structure
wherein the conductive bond ring structure, the MEMS substrate, and the interconnect structure at least partially define a first cavity, wherein the moveable membrane overlies the first cavity and is spaced laterally between sidewalls of the conductive bond ring structure
wherein the first bond structure comprises a first material and the second bond structure comprises a second material different from the first material,
a conductive bond ring structure and a dielectric structure
wherein a thickness of the first bond structure is less than a thickness of the second bond structure.
wherein a thickness of the dielectric structure is less than a thickness of the conductive bond ring structure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21, 25, and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (US 2018/0148327).
Regarding claim 1, Chang (see, e.g., FIG. 1J) discloses an integrated chip, comprising:
a dielectric structure 310 overlying a first substrate 302 (Para 0039);
a second substrate 102, 202a, 202b overlying the dielectric structure 310 and comprising a movable element 202a (Para 0014, Para 0027-Para 0029);
a first bond structure 320 arranged between the dielectric structure 310 and the second substrate 102, 202a, 202b (Para 0042); and
a second bond structure 204 arranged between the dielectric structure 310 and the second substrate 102, 202a, 202b, wherein at least a portion of the movable element 202a is spaced laterally between sidewalls of the second bond structure 204, wherein the first bond structure 320 comprises a first material e.g., germanium and the second bond structure 204 comprises a second material e.g., titanium different form the first material e.g., germanium, wherein a thickness e.g., thickness of 320 of the first bond structure 320 is less than a thickness e.g., thickness of 204 of the second bond structure 204 (Para 0025-Para 0026, Para 0042).
Regarding claim 25, Chang (see, e.g., FIG. 1J) teaches the integrated chip of claim 21, wherein the second bond structure 204 contacts a first conductive interconnect element 312a arranged in the dielectric structure 310, wherein the first bond structure 320 directly overlies at least a portion of the first conductive interconnect element 312a (Para 0042).
Regarding claim 30, Chang (see, e.g., FIG. 1J) teaches the integrated chip of claim 21, wherein a cavity 207 is defined between inner sidewalls e.g., inner sidewalls of 204 of the second bond structure 204 (Para 0029-Para 0032).
Allowable Subject Matter
Claims 31-40 are allowed.
The following is an examiner’s statement of reasons for allowance: Regarding Claim 31, the applied prior art neither anticipates nor renders obvious the claimed integrated chip comprising an upper dielectric structure arranged between the lower dielectric structure and the MEMS structure, wherein the upper dielectric structure comprises opposing inner sidewalls; wherein a top surface of the bond structure is coplanar with a top surface of the upper dielectric structure, and wherein opposing outer sidewalls of the bond structure are spaced between and laterally offset from the opposing inner sidewalls of the upper dielectric structure, in combination with the remaining claimed limitations.
Regarding claim 38, the applied prior art neither anticipates nor renders obvious the claimed integrated chip comprising an upper dielectric structure arranged between the lower dielectric structure and the second substrate, wherein the upper dielectric structure comprises a first dielectric layer on the lower dielectric structure and a second dielectric layer over the first dielectric layer, wherein a material of the first dielectric layer is different from that of the second dielectric layer; wherein the bond structure is spaced laterally between sidewalls of the upper dielectric structure, in combination with the remaining claimed limitations.
Claims 22-24 and 26-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Remarks
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Regarding Claim 31, Chang (US 2018/0148327; see, e.g., FIG. 1J) discloses an integrated chip, comprising: a lower dielectric structure 310 overlying a substrate 302, wherein an electrode 312a is disposed in the lower dielectric structure 310 (Para 0039, Para 0042); a microelectromechanical system (MEMS) structure 102, 202a, 202b over the lower dielectric structure 310 (Para 0014, Para 0027-Para 0029); and a bond structure 204, 320 arranged between the MEMS structure 102, 202a, 202b and the lower dielectric structure 310 (Para 0025-Para 0026, Para 0042).
Regarding claim 38, Chang (US 2018/0148327; see, e.g., FIG. 1J) discloses an integrated chip, comprising: a lower dielectric structure 310 overlying a first substrate 302 (Para 0039); a second substrate 102, 202a, 202b overlying the lower dielectric structure 310 (Para 0014, Para 0027-Para 0029); and a bond structure 204, 320 arranged between the lower dielectric structure 310 and the second substrate 102, 202a, 202b, wherein a cavity 207 is arranged between opposing inner sidewalls of the bond structure 204, 320 (Para 0025-Para 0026, Para 0029-Para 0032, Para 0042).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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