Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/19/2024, 8/2/2024, 8/8/2024, and 4/15/2025 were filed after the mailing date of the Non-final rejection on 7/7/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The formal drawings filed on 7/19/2024 have been approved by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 10-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of U.S. Patent No. 11,264,359. Although the claims at issue are not identical, they are not patentably distinct from each other because both the application and the patent disclose forming a redistribution layer, the forming comprising depositing a first dielectric layer. Forming a first metallization pattern on the first dielectric layer, the first metallization pattern comprising a plurality of conductive traces having a C-shape or U-shape in a plan view. Depositing a second dielectric layer over the first dielectric layer and the first metallization pattern. Forming a second metallization pattern in the second dielectric layer, the second metallization pattern comprising vias connected to the conductive traces of the first metallization pattern; Bonding a first semiconductor die and a second semiconductor die to the redistribution layer. Encapsulating the first and second semiconductor dies with an encapsulant. Bonding the redistribution layer to a package substrate.
Claims 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 11,749,644. Although the claims at issue are not identical, they are not patentably distinct from each other because both the application and the patent disclose a semiconductor die having an active surface with contact pads. A redistribution structure electrically connected to the contact pads of the semiconductor die. The redistribution structure comprising a stress buffer layer comprising a dielectric material. A plurality of metal traces in the dielectric material, each metal trace having a first pattern in a plan view, the first pattern comprising curves with no sharp angles, wherein the first pattern extends between two vertical connections in the redistribution structure. An angle between a first portion of the metal trace extending from a first vertical connection and a line connecting the two vertical connections is in a range of 30° to 150°.
Allowable Subject Matter
4. Claims 1-9 are allowed.
5. The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record teaches or suggest the each conductive trace having a curved shape in a plan view. A second dielectric layer over the first dielectric layer. The second metallization pattern comprising a plurality of vias electrically connected to the conductive traces of the first metallization pattern, wherein the curved shape of each conductive trace comprises at least two curved segments. A first angle between a first curved segment and a line extending through centers of connected vias is in a range of 30° to 150°; and a first semiconductor die and a second semiconductor die over the redistribution structure. in claim 1.
Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
Any comments considered necessary by applicant must be submitted no later
than the payment of the issue fee and, to avoid processing delays, should preferably
accompany the issue fee. Such submissions should be clearly labeled "Comments on
Statement of Reasons for Allowance."
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is 5/1 273-8300.
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AC/July 7, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
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