DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/19/2024, 2/13/2025, 3/26/2025, 10/15/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-5 and 7-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-9, 11, 13 and 15-20 of U.S. Patent No. 12,159,942 in view of Vellianitis (US 2021/0399097).
Regarding claim 1, Pat '942 discloses, in claim 1, an integrated circuit, comprising:
the BEOL semiconductor device including a channel layer, source/drain contacts disposed in connection with the channel layer, connectors disposed in connection with the source/drain contacts, respectively, and first barrier liners which respectively surround the connectors, and which include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners ("a semiconductor device comprising: a channel layer including an oxide semiconductor material; source/drain contacts disposed in connection with the channel layer; connectors disposed in connection with the source/drain contacts, respectively; and first barrier liners which respectively surround the connectors, and which include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners", in claim 1 of Pat '942, is interpreted as the same limitation).
Pat '942 does not explicitly disclose a substrate; a front-end-of-line (FEOL) semiconductor device formed on the substrate; a back-end-of-line (BEOL) semiconductor device formed on the FEOL semiconductor device opposite to the substrate.
Vellianitis teaches, in at least figures 6, 9, and related text, the device comprising a substrate (901, [18]); a front-end-of-line (FEOL) semiconductor device (902/904, [18]) formed on the substrate (901, [18]); a back-end-of-line (BEOL) semiconductor device (960, [16]) formed on the FEOL semiconductor device (902/904, [18]) opposite to the substrate (901, [18]), for the purpose of providing integration structure containing more than one type of semiconductor devices ([14]) thereby increasing density of integration.
Pat '942 and Vellianitis are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '942 with the specified features of Vellianitis because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '942 to have the substrate; the front-end-of-line (FEOL) semiconductor device formed on the substrate; the back-end-of-line (BEOL) semiconductor device formed on the FEOL semiconductor device opposite to the substrate, as taught by Vellianitis, for the purpose of providing integration structure containing more than one type of semiconductor devices ([14], Vellianitis) thereby increasing density of integration.
Regarding claim 2, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 1 as described above.
Pat '942 further discloses, in claim 2, the hydrogen barrier material includes an In-rich oxide material (all limitations are the same with the limitations recited in claim 2 of Pat '942).
Regarding claim 3, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 1 as described above.
Pat '942 further discloses, in claim 3, the hydrogen barrier material includes indium oxide, indium gallium zinc oxide, a semiconductor material including indium, gallium, zinc, silicon, and oxide, tungsten-doped indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, gallium oxide, a metal compound including zinc and nickel, or combinations thereof (all limitations are the same with the limitations recited in claim 3 of Pat '942).
Regarding claim 4, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 1 as described above.
Pat '942 in view of Vellianitis does not explicitly disclose the channel layer has a thickness ranging from 4 nm to 10 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the thickness of the channel layer as claimed in claim 4 in order to optimize the performance of the device in .. It is noted that the selection dimension of the thickness of the channel layer as being no more than use of known technique to improve similar devices in the same way. See MPEP 2143 I. C. It is noted that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill. KSR International Co. v. Teleflex Inc., 550 US 398, 82 USPQ2d 1385, 1389 (2007). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- the channel layer has a thickness ranging from 4 nm to 10 nm) or any unexpected results arising therefrom.
Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Regarding claim 5, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 1 as described above.
Pat '942 further discloses, in claim 5, the BEOL semiconductor device further includes a gate electrode, and a gate dielectric layer disposed between the gate electrode and the channel layer ("further comprising: a gate electrode; and a gate dielectric layer disposed between the gate electrode and the channel layer", in claim 5 of Pat '942, is interpreted as the same limitation).
Regarding claim 7, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 5 as described above.
Pat '942 further discloses, in claim 6, the source/drain contacts are spaced apart from each other and are disposed above the channel layer (all limitations are the same with the limitations recited in claim 6 of Pat '942).
Regarding claim 8, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 7 as described above.
Pat '942 further discloses, in claim 7, the gate electrode is disposed beneath the gate dielectric layer, and the gate dielectric layer is disposed beneath the channel layer (all limitations are the same with the limitations recited in claim 7 of Pat '942).
Regarding claim 9, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 7 as described above.
Pat '942 further discloses, in claim 8, the gate electrode is disposed between the source/drain contacts, and the gate dielectric layer is disposed to surround the gate electrode (all limitations are the same with the limitations recited in claim 8 of Pat '942).
Regarding claim 10, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 9 as described above.
Pat '942 further discloses, in claim 9, the BEOL semiconductor device further includes a second barrier liner located between the gate electrode and the gate dielectric layer, the second barrier liner including the hydrogen barrier material so as to prevent the hydrogen from diffusion through the second barrier liner ("further comprising a second barrier liner located between the gate electrode and the gate dielectric layer, the second barrier liner including the hydrogen barrier material so as to prevent the hydrogen from diffusion through the second barrier liner", in claim 9 of Pat '942, is interpreted as the same limitation).
Regarding claim 11, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 1 as described above.
Vellianitis further teaches, in at least figures 6, 9, and related text, the FEOL semiconductor device (902/904, [18]) is transistor, for the purpose of providing integration structure containing more than one type of semiconductor devices ([14]) thereby increasing density of integration.
Regarding claim 12, Pat '942 discloses, in claim 11, an integrated circuit, comprising:
the BEOL semiconductor device including a channel layer, source/drain contacts disposed in connection with the channel layer, connectors disposed in connection with the source/drain contacts, respectively, and first barrier liners which respectively surround the connectors, and which include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners ("a semiconductor device comprising: a channel layer including an oxide semiconductor material; source/drain contacts disposed in connection with the channel layer; connectors disposed in connection with the source/drain contacts, respectively; and first barrier liners which respectively surround the connectors, and which include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners", in claim 11 of Pat '942, is interpreted as the same limitation).
Pat '942 does not explicitly disclose a substrate; a front-end-of-line (FEOL) semiconductor device formed on the substrate; a back-end-of-line (BEOL) semiconductor device formed on the FEOL semiconductor device opposite to the substrate; each of the connectors having a bottom end with a width that is smaller than a width of a respective one of the source/drain contacts.
Vellianitis teaches, in at least figures 6, 9, and related text, the device comprising a substrate (901, [18]); a front-end-of-line (FEOL) semiconductor device (902/904, [18]) formed on the substrate (901, [18]); a back-end-of-line (BEOL) semiconductor device (960, [16]) formed on the FEOL semiconductor device (902/904, [18]) opposite to the substrate (901, [18]); each of the connectors (176/178, [32]) having a bottom end with a width that is smaller than a width of a respective one of the source/drain contacts (160, [32]) (figures), for the purpose of providing integration structure containing more than one type of semiconductor devices ([14]) thereby increasing density of integration.
Pat '942 and Vellianitis are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '942 with the specified features of Vellianitis because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '942 to have the substrate; the front-end-of-line (FEOL) semiconductor device formed on the substrate; the back-end-of-line (BEOL) semiconductor device formed on the FEOL semiconductor device opposite to the substrate; each of the connectors having a bottom end with a width that is smaller than a width of a respective one of the source/drain contacts, as taught by Vellianitis, for the purpose of providing integration structure containing more than one type of semiconductor devices ([14], Vellianitis) thereby increasing density of integration.
Regarding claim 13, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 12 as described above.
Vellianitis further teaches, in at least figures 6, 9, and related text, an interconnect-level structure (908, [19]) disposed between the FEOL semiconductor device (902/904, [18]) and the BEOL semiconductor device (960, [16]), for the purpose of providing integration structure containing more than one type of semiconductor devices ([14]) thereby increasing density of integration.
Regarding claim 14, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 12 as described above.
Pat '942 further discloses, in claim 13, the hydrogen barrier material includes indium oxide, indium gallium zinc oxide, a semiconductor material including indium, gallium, zinc, silicon, and oxide, tungsten-doped indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, gallium oxide, a metal compound including zinc and nickel, or combinations thereof (all limitations are the same with the limitations recited in claim 13 of Pat '942).
Regarding claim 15, Pat '942 discloses, in claim 15, a method for manufacturing an integrated circuit, comprising: forming a channel layer; forming source/drain contacts over the channel layer; forming connectors which are disposed in connection with the source/drain contacts, respectively; and forming first barrier liners which respectively surround the connectors, and which include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners ("a method for manufacturing a semiconductor device, comprising: forming a channel layer which includes an oxide semiconductor material; forming source/drain contacts over the channel layer to be in connection with the channel layer; forming connectors which are disposed in connection with the source/drain contacts, respectively; and forming first barrier liners which respectively surround the connectors, and which include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners", in claim 15 of Pat '942, is interpreted as the same limitation).
Pat '942 does not explicitly disclose forming a channel layer above a substrate; forming source/drain contacts over the channel layer opposite to the substrate.
Vellianitis teaches, in at least figures 6, 9, and related text, the method comprising forming a channel layer (131, [23]) above a substrate (901, [18]); forming source/drain contacts (160, [32]) over the channel layer (131, [23]) opposite to the substrate (901, [18]) (figures), for the purpose of providing integration structure containing more than one type of semiconductor devices ([14]) thereby increasing density of integration.
Pat '942 and Vellianitis are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '942 with the specified features of Vellianitis because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '942 to have the forming a channel layer above a substrate; the forming source/drain contacts over the channel layer opposite to the substrate, as taught by Vellianitis, for the purpose of providing integration structure containing more than one type of semiconductor devices ([14], Vellianitis) thereby increasing density of integration.
Regarding claim 16, Pat '942 in view of Vellianitis discloses the method of claim 15 as described above.
Pat '942 further discloses, in claim 16, forming a gate electrode; and forming a gate dielectric layer such that the gate dielectric layer is disposed between the gate electrode and the channel layer (all limitations are the same with the limitations recited in claim 16 of Pat '942).
Regarding claim 17, Pat '942 in view of Vellianitis discloses the method of claim 16 as described above.
Pat '942 further discloses, in claim 17, the gate electrode is formed between the source/drain contacts, and the gate dielectric layer is formed to surround the gate electrode (all limitations are the same with the limitations recited in claim 17 of Pat '942).
Regarding claim 18, Pat '942 in view of Vellianitis discloses the method of claim 17 as described above.
Pat '942 further discloses, in claim 18, forming a second barrier liner between the gate electrode and the gate dielectric layer, the second barrier liner including the hydrogen barrier material so as to prevent the hydrogen from diffusion through the second barrier liner to the channel layer (all limitations are the same with the limitations recited in claim 18 of Pat '942).
Regarding claim 19, Pat '942 in view of Vellianitis discloses the method of claim 15 as described above.
Pat '942 further discloses, in claim 19, the hydrogen barrier material includes indium oxide, indium gallium zinc oxide, a semiconductor material including indium, gallium, zinc, silicon, and oxide, tungsten-doped indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, gallium oxide, a metal compound including zinc and nickel, or combinations thereof (all limitations are the same with the limitations recited in claim 19 of Pat '942).
Regarding claim 20, Pat '942 in view of Vellianitis discloses the method of claim 15 as described above.
Pat '942 further discloses, in claim 20, the source/drain contacts include cobalt, tungsten, copper, titanium, tantalum, aluminum, zirconium, hafnium, or combinations thereof (all limitations are the same with the limitations recited in claim 20 of Pat '942).
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5 of U.S. Patent No. 12,159,942 in view of Vellianitis (US 2021/0399097), and further in view of Ohguro (US 2015/0249156).
Regarding claim 6, Pat '942 in view of Vellianitis discloses the integrated circuit of claim 5 as described above.
Pat '942 in view of Vellianitis does not explicitly disclose at least one of the gate electrode and the gate dielectric layer has a width that is different from a width of the channel layer.
Ohguro teaches, in at least figure 1 and related text, the device comprising at least one of the gate electrode (10, [26]) and the gate dielectric layer (210, [26]) has a width that is different from a width of the channel layer (220, [26]), for the purpose of providing semiconductor devices capable of suppressing deterioration of threshold voltage ([23]).
Pat '942, Vellianitis, and Ohguro are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '942 in view of Vellianitis with the specified features of Ohguro because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '942 in view of Vellianitis to have the at least one of the gate electrode and the gate dielectric layer having a width that is different from a width of the channel layer, as taught by Ohguro, for the purpose of providing semiconductor devices capable of suppressing deterioration of threshold voltage ([23], Ohguro).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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