DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment/Restriction
Applicant’s election without traverse of Group I and Claims 1-5 in the reply filed on August 26, 2026 is acknowledged. Thus, Claims 6-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on August 26, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 1, the limitation “the first high-pressure region N-diffusion region of the lower area” lacks sufficient antecedent basis.. Thus, the limitation render the claims indefinite and clarification is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 9,905,687 B1 to Zhu et al. (“Zhu”) in view of U.S. Patent No. 8,716,791 B1 to Iravani et al. (“Iravani”). . As to claim 1, although Zhu discloses a method for improving ESD performance of a metal-gate high-voltage device, at least comprising: step I. providing a P-substrate (13), and forming a high voltage P-well (17, 70) on the P-substrate (13); Step II. forming a first STI region (66/75) and a second STI region (66/75) spaced apart from each other within the high voltage P-well (17, 70), wherein the high voltage P-well (17, 70) between the first STI region (66/75) and the second STI region (66/75), and the high voltage P-well (17, 70) on side of the first STI region (66/75) away from the second STI region (66/75), and the high voltage P-well (17, 70) on side of the second STI region (66/75) away from the first STI region (66/75), are active regions; Step III. forming a first high-voltage region N-diffusion region (80) within the high voltage P-well (17, 70) between the first STI region (66/75), and second STI region (66/75); and Step VI. forming an IO N-well (52) within the first high-pressure region N-diffusion region of the lower area (See Fig. 12, Fig. 13, Fig. 14, Column 2, lines 30-65, Column 7, lines 31-67, Column 8, lines 1-60), Zhu does not further disclose Step IV. etching the active region between the first STI region and second STI region to form recesses in the area immediately adjacent to the first STI region and the area immediately adjacent to the second STI region between the first STI region and second STI region; and etching the active region at the side of the first STI region away from the second STI region and the active region at the side of the second STI region away from the first STI region to form a recess; Step V. filling the recesses with silicon oxide, wherein the silicon oxide in the recess in the side of the first STI region away from the second STI region and the silicon oxide in the recess in the side of the second STI region away from the first STI region are formed as a gate oxide layer; and the silicon oxide in the recess immediately adjacent to the first STI region between the first STI region and second STI region is formed as a first silicon oxide structure, and the silicon oxide in the recess immediately adjacent to the second STI region between the first STI region and second STI region is formed as a second silicon oxide structure; and forming the IO N-well within the first high-pressure region N-diffusion region of the lower area between the first silicon oxide structure and second silicon oxide structure. However, Iravani does disclose Step IV. etching the active region (312) to form recesses under the gate (324) and away from the gate (324); Step V. filling the recesses with silicon oxide, wherein the silicon oxide in the recesses are formed as a gate oxide layer, a first silicon oxide structure, and a second silicon oxide structure (See Fig. 3-Fig. 5, Column 7, lines 41-67, Column 8, lines 1-53). In view of the teaching of Iravani, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Zhu to have Step IV. etching the active region between the first STI region and second STI region to form recesses in the area immediately adjacent to the first STI region and the area immediately adjacent to the second STI region between the first STI region and second STI region; and etching the active region at the side of the first STI region away from the second STI region and the active region at the side of the second STI region away from the first STI region to form a recess; Step V. filling the recesses with silicon oxide, wherein the silicon oxide in the recess in the side of the first STI region away from the second STI region and the silicon oxide in the recess in the side of the second STI region away from the first STI region are formed as a gate oxide layer; and the silicon oxide in the recess immediately adjacent to the first STI region between the first STI region and second STI region is formed as a first silicon oxide structure, and the silicon oxide in the recess immediately adjacent to the second STI region between the first STI region and second STI region is formed as a second silicon oxide structure; and forming the IO N-well within the first high-pressure region N-diffusion region of the lower area between the first silicon oxide structure and second silicon oxide structure because the additional the gate oxide layer and the first and second silicon oxide structures in addition to the first and second STI regions serve to increase resistivity in the extended active region to allow for an increased drive current (See Column 8, lines 16-36).
As to claim 2, Zhu further discloses wherein: a third STI region (66/71) and a fourth STI region (66/71) are also formed within the high voltage P-well (17, 70) in step II, wherein the third STI region (66/71) is located at a side of the first STI region (66/75) away from the second STI region (66/75), the fourth STI region (66/71) is located at a side of the second STI region (66/75) away from the first STI region (66/75), and the high voltage P-well between (17, 70) the third STI region (66/71) and first STI region (66/75) and the high voltage P-well (17, 70) between the second STI region (66/75) and fourth STI region (66/71) are active regions (See Fig. 13). As to claim 3, Zhu further discloses wherein in step III, a second high-voltage region N-diffusion region (50) and a first high-voltage region P-diffusion region (44) adjacent to each other are formed in the active region between the third STI region (66/71) and first STI region (66/75); and a third high-voltage region N-diffusion region (50) and a second high-pressure region P-diffusion region (44) adjacent to each other are formed in the active region between the second STI region (66/75) and fourth STI region (66/71) (See Fig. 13).
As to claim 4, Zhu in view of Iravani further discloses wherein the method further comprises step VII. forming a metal gate (342) on the gate oxide layer (320, 322) (See Iravani Fig. 7, Column 9, lines 45-54).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVID CHEN/Primary Examiner, Art Unit 2815
