Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS)s submitted on July 19, 2024 and September 5, 2024 were filed before the mailing of a first Office action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner notes that claims 2-21 are directed toward methods of fabrication.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 2-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 12,159,925. Although the claims at issue are not identical, they are not patentably distinct from each other because the features found in claims 2-3 of the present application are anticipated by claims 1-3 of U.S. Patent No 12,159,925.
Regarding Claim 2:
The combination of claims 1-3 of the ‘925 Patent discloses a method comprising:
forming a semiconductor layer on a semiconductor substrate, the semiconductor layer and the semiconductor substrate having mismatched lattice constants (forming a semiconductor layer on a semiconductor substrate, the semiconductor layer and the semiconductor substrate having mismatched lattice constants, See claim 2 lines 56-58);
patterning the semiconductor layer to form a first semiconductor fin and a second semiconductor fin, the first semiconductor fin having a first germanium concentration, the second semiconductor fin having a second germanium concentration (patterning the semiconductor layer and the semiconductor substrate, the first semiconductor fin comprising first patterned portions of the semiconductor layer and the semiconductor substrate, the second semiconductor fin comprising second patterned portions of the semiconductor layer and the semiconductor substate, See claim 2 lines 59-64 and the semiconductor layer comprises silicon germanium, See claim 3 lines 66-67);
increasing the first germanium concentration of the first semiconductor fin and the second germanium concentration of the second semiconductor fin by performing a first oxidation process on the first semiconductor fin and the second semiconductor fin (increasing the first germanium concentration of the first semiconductor fin and the second germanium concentration of the second semiconductor fin by oxidizing first sidewalls of the first semiconductor fin and second sidewalls of the second semiconductor fin, See claim 1 lines 41-45); and
increasing the second germanium concentration of the second semiconductor fin by performing a second oxidation process on the second semiconductor fin while the first semiconductor fin is masked, the second oxidation process being different from the first oxidation process (masking the first semiconductor fin and increasing the second germanium concentration of the second semiconductor fin by oxidizing the second sidewalls of the second semiconductor fin, the first sidewalls of the first semiconductor fin being masked when oxidizing the second sidewalls of the second semiconductor fin, See claim 1 lines 46-52. The examiner notes the claim term different is interpreted to mean distinct.)
Regarding Claim 3:
The combination of claim 1-3 of the ‘925 Patent discloses wherein the semiconductor layer comprises silicon germanium (the semiconductor layer comprises silicon germanium, See claim 3 lines 66-67).
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 12,159,925 in view of Cheng et al. (US 2018/0247938).
Regarding Claim 4:
The combination of claims 1-3 of the ‘925 patent discloses the method of claim 2.
The combination of claim 1-3 does not disclose before performing the first oxidation process, forming an isolation region adjacent the first semiconductor fin and the second semiconductor fin.
Cheng discloses before performing the first oxidation process, forming an isolation region adjacent the first semiconductor fin and the second semiconductor fin (before oxidizing the fin layer pillars of the left vertical fin and the right vertical fin, forming filler layer in the spaces adjacent to the left vertical fin and the right vertical, See fig. 12, ref. no. 190 and paragraphs 95-97).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of claims 1-3 of the ‘925 patent to include before performing the first oxidation process, forming an isolation region adjacent the first semiconductor fin and the second semiconductor fin as taught by Cheng so that the chemical compositions of the lower portions of the first semiconductor fin and the second semiconductor fin are not changed during the subsequent oxidation process.
Claims 5 and 7-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 12,159,925 in view of Mao (US 2017/0200810).
Regarding Claim 5:
The combination of claims 1-3 of the ‘925 patent discloses the method of claim 2.
The combination of claim 1-3 does not disclose after performing the first oxidation process, forming an isolation region adjacent the first semiconductor fin and the second semiconductor fin.
Mao after performing the first oxidation process, forming an isolation region adjacent the first semiconductor fin and the second semiconductor fin (after the oxidation process the right two fins and the left two fins, forming an insolation layer adjacent to the fins, See fig. 2, ref. nos. 103, 111, 112, and paragraphs 26-27 for the first oxidization process of the right two fins and the left two fins, See fig. 10, ref. nos. 118, paragraphs 58-59 and 73 for forming an isolation layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify claims 1-3 of the ‘925 patent to include after performing the first oxidation process, forming an isolation region adjacent the first semiconductor fin and the second semiconductor fin as taught by Mao in improve the interface between the isolation region and the fins. (See Mao paragraph 30.)
Regarding Claim 7:
The combination of claims 1-3 of the ‘925 patent discloses the method of claim 2.
The combination of claim 1-3 does not disclose after performing the second oxidation process, a width of the second semiconductor fin is less than a width of the first semiconductor fin.
Mao discloses after performing the second oxidation process, a width of the second semiconductor fin is less than a width of the first semiconductor fin (the thickness of the right two fins that are not covered by the barrier layer is less than the thickness of the left fins that are covered by the barrier layer after oxidizing the right two fins a second time, See Mao fig. 10, ref. nos. 111, 112 and paragraph 65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify claims 1-3 of the ‘925 patent to include after performing the second oxidation process, a width of the second semiconductor fin is less than a width of the first semiconductor fin as taught by Mao in order to form the first semiconductor fin and the second semiconductor fin with different dimensions. (See Mao paragraphs 7 and 65).
Regarding Claim 8:
The combination of claims 1-3 of the ‘925 patent discloses the method of claim 2.
The combination of claims 1-3 does not disclose wherein the first oxidation process and the second oxidation process each comprise an in-situ steam generation process.
Mao discloses the first oxidation process is an in-situ steam generation process, (See fig. 2, ref. nos. 103, 111, 112, and paragraph 31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of claims 1-3 of the ‘925 patent to include the first oxidation process is an in-situ steam generation process as taught by Mao in order form a uniform oxide layer.
The above stated combination of claims 1-3 of the ‘925 Patent and Mao does not disclose wherein the second oxidation process comprises an in-situ steam generation process.
Mao discloses an oxidation process is an in-situ steam generation process, (See fig. 2, ref. nos. 103, 111, 112, and paragraph 31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of claim 1-3 of the ‘925 patent and Mao to include the second oxidation process is an in-situ steam generation process as taught by Mao for ease of fabrication of the right vertical fin in that repeating the same oxidation process does not require different fabrication equipment or materials.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-8 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2018/0247938) in view of Mao (US 2017/0200810).
Regarding Claim 2:
Cheng discloses a method comprising:
forming a semiconductor layer on a semiconductor substrate (forming fin layer on a semiconductor substrate, See fig. 4, ref. nos. 110, 130, paragraphs 43 and 52-53), the semiconductor layer and the semiconductor substrate having mismatched lattice constants (the fin layer is made of silicon germanium and the semiconductor substrate is formed of silicon, See paragraphs 43 and 55. The examiner notes that silicon germanium and silicon have different lattice constants.);
patterning the semiconductor layer to form a first semiconductor fin and a second semiconductor fin (patterning the fin layer to form a left vertical fin and a right vertical fin, See fig. 11, ref. no. 111 and paragraphs 85-88), the first semiconductor fin having a first germanium concentration (the left vertical fin has a germanium concentration because the left vertical fin is formed from the silicon germanium fin layer, See fig. 11, ref. no. 131, paragraphs 55 and 87-88), the second semiconductor fin having a second germanium concentration (the right vertical fin has a germanium concentration because the right vertical fin is formed from the silicon germanium fin layer, See fig. 11, ref. no. 131, paragraphs 55 and 87-88);
increasing the first germanium concentration of the first semiconductor fin and the second germanium concentration of the second semiconductor fin by performing a first oxidation process on the first semiconductor fin and the second semiconductor fin (increasing the germanium concentration in the pillar cores of the left vertical fin and the right vertical fin by oxidizing the fin layer pillars of the left vertical fin and the right vertical fin, See fig. 13, ref. nos. 131, fig. 14, ref. nos. 133, 135, and paragraphs 105-108).
Cheng does not disclose increasing the second germanium concentration of the second semiconductor fin by performing a second oxidation process on the second semiconductor fin while the first semiconductor fin is masked, the second oxidation process being different from the first oxidation process. (The examiner notes the claim term different is interpreted to mean distinct.)
Mao discloses oxidizing the right two fins a second time while the left two fins are covered by a barrier layer with the second time the right two fins are oxidized occurring after the first oxidization process of the right two fins and the left two fins has ended (See fig. 2, ref. nos. 103, 111, 112, and paragraphs 26-27 for the first oxidization process of the right two fins and the left two fins, See fig. 8, ref. nos. 106, 111, 112, 122, and paragraphs 62-65 for the second time the right two fins are oxidized after the first oxidization process has ended).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cheng to include repeat oxidizing the right vertical fin a second time while the left vertical fin is covered by a barrier layer as taught by Mao in order to form the right vertical fin and the left vertical fin with different dimensions. (See Mao paragraphs 7 and 65).
The examiner notes that the combination of Cheng and Mao discloses increasing the second germanium concentration of the second semiconductor fin by performing a second oxidation process on the second semiconductor fin while the first semiconductor fin is masked, the second oxidation process being different from the first oxidation process because repeating the oxidizing process on the right vertical fin a second time while the left vertical fin is covered by a barrier layer will further increase the germanium concentration in the pillar core of the right vertical fin (See Cheng fig. 14, ref. no. 135 and paragraphs 105-108).
Regarding Claim 3:
Cheng discloses wherein the semiconductor layer comprises silicon germanium (the fin layer is made of silicon germanium, See paragraphs 55).
Regarding Claim 4:
Cheng discloses before performing the first oxidation process, forming an isolation region adjacent the first semiconductor fin and the second semiconductor fin (before oxidizing the fin layer pillars of the left vertical fin and the right vertical fin, forming filler layer in the spaces adjacent to the left vertical fin and the right vertical, See fig. 12, ref. no. 190 and paragraphs 95-97).
Regarding Claim 5:
The above stated combination of Cheng and Mao discloses the above stated method.
The above stated combination of Cheng and Mao does not disclose after performing the first oxidation process, forming an isolation region adjacent the first semiconductor fin and the second semiconductor fin.
Mao after performing the first oxidation process, forming an isolation region adjacent the first semiconductor fin and the second semiconductor fin (after the oxidation process the right two fins and the left two fins, forming an insolation layer adjacent to the fins, See fig. 2, ref. nos. 103, 111, 112, and paragraphs 26-27 for the first oxidization process of the right two fins and the left two fins, See fig. 10, ref. nos. 118, paragraphs 58-59 and 73 for forming an isolation layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cheng and Mao to include after performing the first oxidation process, forming an isolation region adjacent the first semiconductor fin and the second semiconductor fin as taught by Mao in order to improve the interface between the isolation region and the fins. (See Mao paragraph 30)
Regarding Claim 6:
The above stated combination of Cheng and Mao discloses after performing the second oxidation process, forming a metal gate on the second semiconductor fin (forming a metal gate electrode on the right vertical fin after completion of the processing of the right vertical fin, See Cheng figs. 20-21, ref. nos. 210, 220, paragraphs 134-135 and 137-138).
Regarding Claim 7:
The above stated combination of Cheng and Mao discloses wherein after performing the second oxidation process, a width of the second semiconductor fin is less than a width of the first semiconductor fin (the thickness of the right two fins that are not covered by the barrier layer is less than the thickness of the left fins that are covered by the barrier layer after oxidizing the right two fins a second time, See Mao fig. 10, ref. nos. 111, 112 and paragraph 65).
Regarding Claim 8:
The above stated combination of Cheng and Mao discloses the above stated method.
The above stated combination of Cheng and Mao does not disclose wherein the first oxidation process and the second oxidation process each comprise an in-situ steam generation process.
Mao discloses the first oxidation process is an in-situ steam generation process, (See fig. 2, ref. nos. 103, 111, 112, and paragraph 31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cheng and Mao to include the first oxidation process is an in-situ steam generation process as taught by Mao in order to form a uniform oxide layer.
The above stated combination of Cheng and Mao does not disclose wherein the second oxidation process comprises an in-situ steam generation process.
Mao discloses an oxidation process is an in-situ steam generation process, (See fig. 2, ref. nos. 103, 111, 112, and paragraph 31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cheng and Mao to include the second oxidation process is an in-situ steam generation process as taught by Mao for ease of fabrication of the right vertical fin in that repeating the same oxidation process does not require different fabrication equipment or materials.
Claims 9-10, 12-18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Jambunathan et al. (WO 2019/066857) in view of Li (US 2018/0108574) further in view of Cheng et al. (US 2018/0247938).
Regarding Claim 9:
Jambunathan discloses a method comprising:
forming a semiconductor fin extending from a substrate (patterning the silicon germanium layer on a silicon substrate to form a rightmost fin, See fig. 2B, page 6 lines 16-21, page 8 lines 13-17, and page 9 lines 13-33), the semiconductor fin having a germanium concentration (the rightmost fin has a germanium concentration because the rightmost fin is formed from silicon germanium, See fig. 2B and page 8 lines 13-17);
forming a dummy gate on sidewalls of the semiconductor fin (forming a dummy gate stack on the rightmost fin, See fig. 2D, ref. nos. 252, 254, page 12 lines 3-25);
forming a spacer adjacent the dummy gate (forming spacers on the side of the dummy gate stack, See fig. 2D, ref. nos. 250, 252, 254, page 12 lines 26-33 and page 13 lines 1-2);
removing the dummy gate from the semiconductor fin (removing the dummy gate stack from the rightmost fin, See fig. 2F and page 14 lines 3-9);
after removing the dummy gate, oxidizing the sidewalls of the semiconductor fin (oxidizing the rightmost fin, See figs. 2F, 3A, page 14 lines 31-34 and page 15 lines 1-17); and
forming a metal gate on the sidewalls of the semiconductor fin (forming a gate electrode made of metal on the rightmost fin, See figs. 3C, 4A, ref. no. 284, page 20 lines 8-22, 33, and page 21 lines 1-2).
Jambunathan does not disclose growing an epitaxial source/drain region adjacent to the spacer and increasing the germanium concentration of the semiconductor fin by oxidizing the sidewalls of the semiconductor fin.
Li discloses growing an epitaxial source/drain region adjacent to the spacer (growing epitaxial layers on a first lightly doped source/drain region, See fig. 13, ref. nos. 110, 221, fig. 14, ref. no. 231, paragraphs 51 and 57-59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Jambunathan to include growing an epitaxial source/drain region adjacent to the spacer as taught by Li in order to enhance the electrical performance of the finFET. (See Li paragraph 17).
The above stated combination of Jambunathan and Li does not disclose increasing the germanium concentration of the semiconductor fin by oxidizing the sidewalls of the semiconductor fin.
Cheng discloses increasing the germanium concentration of the semiconductor fin by oxidizing the sidewalls of the semiconductor fin (increasing the germanium concentration in the pillar core the right vertical fin by oxidizing the fin layer pillar of the right vertical fin, See fig. 13, ref. nos. 131, fig. 14, ref. nos. 133, 135, and paragraphs 105-108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Jambunathan and Li to include increasing the germanium concentration of the semiconductor fin by oxidizing the sidewalls of the semiconductor fin as taught by Cheng in order to increase carrier mobility in the channel region.
Regarding Claim 10:
The above stated combination of Jambunathan, Li, and Cheng discloses wherein oxidizing the sidewalls of the semiconductor fin forms an oxide layer on the sidewalls of the semiconductor fin (oxidizing the fin layer pillar of the right vertical forms a silicon oxide layer on the pillar core, See Cheng fig. 14, ref. nos. 133, 135 and paragraph 10), the method further comprising: removing the oxide layer before forming the metal gate (etching the rightmost fin to achieve a trimmed rightmost fin, See Jambunathan figs. 3A, ref. nos. 210, 211, fig. 3B, ref. no. 213, page 15 lines 29-35, and page 16 lines 1-12).
Regarding Claim 12:
The above stated combination of Jambunathan, Li, and Cheng discloses the semiconductor fin comprises a lower portion (lower portion of the fin native to the substrate, See Jambunathan figs. 2B, 3B, ref. nos. 200, 205, and page 9 lines 29-33) and an upper portion (upper/channel region, See Jambunathan fig. 3B, ref. no. 213 page 15 lines 29-35, and page 16 lines 1-12), and wherein the upper portion has a higher germanium concentration than the lower portion after increasing the germanium concentration (after oxidizing the rightmost fin the germanium concentration in the substrate pillar can remain as the substrate germanium concentration, that is essentially 0% germanium, See Cheng paragraph 104).
Regarding Claim 13:
The above stated combination of Jambunathan, Li, and Cheng discloses the lower portion of the semiconductor fin comprises silicon (lower portion of the fin native to the substrate comprises silicon because the substrate is formed from silicon, See Jambunathan page 8 lines 13-17, and page 9 lines 13-33) and the upper portion of the semiconductor fin comprises silicon germanium (the pillar is formed from silicon germanium, See Cheng paragraph 108).
Regarding Claim 14:
The above stated combination of Jambunathan, Li, and Cheng discloses forming a lightly doped source/drain region in the semiconductor fin (forming the first lightly doped source/drain region in fin, See Li fig. 13, ref. nos. 102, 221, and paragraphs 45-51), and wherein the epitaxial source/drain region is grown in the lightly doped source/drain region spacer (growing epitaxial layers on a first lightly doped source/drain region, See Li fig. 13, ref. nos. 110, 221, fig. 14, ref. no. 231, paragraphs 51 and 57-59).
Regarding Claim 15:
The above stated combination of Jambunathan, Li, and Cheng discloses wherein oxidizing the sidewalls of the semiconductor fin forms a germanium-rich layer (surface layer of the pillar core that has a higher germanium concentration than the inner portion of the pillar core, See Cheng, fig. 14, ref. no. 135 and paragraph 112) and the lightly doped source/drain region is formed in the germanium-rich layer (the first light doped source/drain region is formed in the portion of the fin underneath the first gate structure, See Li fig. 13, ref. nos. 102, 110, and 221).
Regarding Claim 16:
The above stated combination of Jambunathan, Li, and Cheng discloses wherein the semiconductor fin has a first width (initial width, See Cheng, fig. 13, ref. no. W1) before oxidizing the sidewalls and a second width (final width, See Cheng, fig. 13, ref. no. W2) after oxidizing the sidewalls, the second width being less than the first width (the final width is less than the initial width, See Cheng, fig. 13, ref. nos. W1, W2, and paragraph 110).
Regarding Claim 17:
Jambunathan discloses a method comprising:
forming a first channel region having a first germanium concentration (patterning the silicon germanium layer on a silicon substrate to form a rightmost fin, See fig. 2B, page 6 lines 16-21, page 8 lines 13-17, and page 9 lines 13-33. The examiner notes that pattering the silicon germanium layer on a silicon substrate to form a rightmost fin includes the portion of the rightmost fin that is in a channel region of the finFET. The examiner also notes that the first channel region has a germanium concentration because the rightmost fin is formed from silicon germanium.);
forming a dummy gate on the first channel region (forming a dummy gate stack on the rightmost fin, See fig. 2D, ref. nos. 252, 254, page 12 lines 3-25);
forming a spacer adjacent the dummy gate (forming spacers on the side of the dummy gate stack, See fig. 2D, ref. nos. 250, 252, 254, page 12 lines 26-33 and page 13 lines 1-2);
removing the dummy gate from the first channel region (removing the dummy gate stack from the rightmost fin, See fig. 2F and page 14 lines 3-9);
after removing the dummy gate, oxidizing the sidewalls of the first channel region (oxidizing the rightmost fin, See figs. 2F, 3A, page 14 lines 31-34 and page 15 lines 1-17); and
forming a metal gate on the first channel region (forming a gate electrode made of metal on the rightmost fin, See figs. 3C, 4A, ref. no. 284, page 20 lines 8-22, 33, and page 21 lines 1-2).
Jambunathan does not disclose growing an epitaxial source/drain region adjacent to the spacer and the first channel region and increasing the germanium concentration of the first channel region.
Li discloses growing an epitaxial source/drain region adjacent to the spacer and the first channel region (growing epitaxial layers on a first lightly doped source/drain region, See fig. 13, ref. nos. 110, 221, fig. 14, ref. no. 231, paragraphs 51 and 57-59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Jambunathan to include growing an epitaxial source/drain region adjacent to the spacer and the first channel region as taught by Li in order to enhance the electrical performance of the finFET. (See Li paragraph 17).
The above stated combination of Jambunathan and Li does not disclose increasing the germanium concentration of the first channel region.
Cheng discloses increasing the germanium concentration of the first channel region (increasing the germanium concentration in the pillar core the right vertical fin by oxidizing the fin layer pillar of the right vertical fin, See fig. 13, ref. nos. 131, fig. 14, ref. nos. 133, 135, and paragraphs 105-108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Jambunathan and Li to include increasing the germanium concentration of the first channel as taught by Cheng in order to increase carrier mobility in the channel region.
Regarding Claim 18:
The above stated combination of Jambunathan, Li, and Cheng discloses wherein the dummy gate comprises a dummy dielectric (the dummy gate stack structure includes a dummy gate dielectric, See Jambunathan fig. 2D, ref. no. 252 and page 12 lines 12-25) and increasing the first germanium concentration of the first channel region comprises:
after removing the dummy dielectric of the dummy gate (oxidizing the rightmost fin after the dummy gate dielectric, See fig. 2F, 3A, and page 14 lines 3-9, 31-34 and page 15 lines 1-17); forming an oxide layer on the first channel region (oxidizing the fin layer pillar of the right vertical forms a silicon oxide layer on the pillar core, See Cheng fig. 14, ref. nos. 133, 135 and paragraph 10); and
removing the oxide layer from the first channel region (etching the rightmost fin to achieve a trimmed upper channel region, See figs. 3A, ref. nos. 210, 211, fig. 3B, ref. no. 213, page 15 lines 29-35, and page 16 lines 1-12).
Regarding Claim 21:
The above stated combination of Jambunathan, Li, and Cheng discloses wherein the epitaxial source/drain region comprises p-type dopant (p-type ions are doped in the first epitaxial layers, See Li fig. ref. no. 231 and paragraph 60).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jambunathan et al. (WO 2019/066857), Li (US 2018/0108574), and Cheng et al. (US 2018/0247938) in view of Abe et al. (JPH 08195494 A). The examiner notes that the citations to paragraphs of Abe refer to paragraphs of the attached English language translation.
Regarding Claim 11:
The above stated combination of Jambunathan, Li, and Cheng discloses the above stated method. Cheng further discloses the use of ozone and water as oxidizing agents (See paragraph 108).
The above stated combination of Jambunathan, Li, and Cheng does not disclose wherein oxidizing the sidewall of the semiconductor fin comprises performing a rapid thermal anneal with water or ozone.
Abe discloses performing a rapid thermal anneal with water vapor or ozone to form an oxide film (See fig. 3 and paragraphs 59-61).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Jambunathan, Li, and Cheng to include performing a rapid thermal anneal with water vapor or ozone to for an oxide film as taught by Abe in order to form a uniform oxide film. (See Abe paragraph 61).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jambunathan et al. (WO 2019/066857), Li (US 2018/0108574), and Cheng et al. (US 2018/0247938) in view of Mao (US 2017/0200810).
Regarding Claim 19:
The above stated combination of Jambunathan, Li, and Cheng discloses the above stated method. Jambunathan further discloses forming a second channel region having a second germanium concentration (patterning the silicon germanium layer on a silicon substrate to form a second rightmost fin, See fig. 2B, page 6 lines 16-21, page 8 lines 13-17, and page 9 lines 13-33. The examiner notes that pattering the silicon germanium layer on a silicon substrate to form a second rightmost fin includes the portion of the second rightmost fin that is in a channel region of the finFET. The examiner also notes that the second channel region has a germanium concentration because the second rightmost fin is formed from silicon germanium.)
The above stated combination of Jambunathan, Li, and Cheng does not disclose wherein the second germanium concentration of the second channel is not increase when increasing the first germanium concentration of the first channel region.
Mao discloses oxidizing the right two fins time while the left two fins are covered by a barrier layer (See fig. 8, ref. nos. 106, 111, 112, 122, and paragraphs 62-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Jambunathan, Li, and Cheng to include oxidizing the rightmost fin while the second rightmost fin is covered by a barrier layer as taught by Mao in order to form the rightmost fin and the second rightmost fin with different dimensions. (See Mao paragraphs 7 and 65).
The examiner notes that the combination of Jambunathan, Li, Cheng, and Mao discloses increasing the second germanium concentration of the second semiconductor fin by performing an oxidation process on the second semiconductor fin while the first semiconductor fin is masked because oxidizing process on the rightmost fin while the second rightmost fin is covered by a barrier layer will further increase the germanium concentration in the pillar core of the rightmost fin (See Cheng fig. 14, ref. no. 135 and paragraphs 105-108).
Regarding Claim 20:
The above stated combination of Jambunathan, Li, Cheng, and Mao discloses wherein a width of the first channel region is less than a width of the second channel region (the thickness of the right two fins that are not covered by the barrier layer is less than the thickness of the left fins that are covered by the barrier layer after oxidizing the right two fins a second time, See Mao fig. 10, ref. nos. 111, 112 and paragraph 65).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRETT SQUIRES whose telephone number is (571)272-8214. The examiner can normally be reached Mon-Fri 8:00am-5:30pm.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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