DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawings
Regarding Fig.3, there should be a downward arrow from step S1 to step S2; the arrow from step S5 to step 6 should be a downward arrow, not an upward arrow.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office Action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office Action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office Action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bell et al. (US7005386).
Regarding claim 1, Bell discloses a polysilicon gate etch method (abstract), comprising the following steps: S1: sequentially forming a gate oxide layer (gate dielectric 210 is a silicon oxide, lines 38-42 and line 67, column 3; line 1, column 4; Fig. 2A), a polysilicon layer (gate electrode 208 comprises polysilicon, lines 38-42 and lines 63-64, column 3; Fig. 2A), a hard mask layer (layer 206, lines 38-42, column 3; Fig. 2A), a bottom anti reflection coating (layer 204, lines 38-42, column 3; Fig. 2A), and a photoresist on a silicon substrate (layer 202, lines 38-45, column 3; substrate 212 is a silicon substrate, line 9, column 4; Fig. 2A); S2: photoetching the photoresist according to design linewidths of polysilicon gates at various positions on a wafer (forming a patterned photoresist mask inherently involves photoetching the photoresist, lines 38-45, column 3; Fig. 2A ); S3: injecting an etch gas into an etch chamber, to remove the bottom anti reflection coating outside a polysilicon gate area by etch and retain the bottom anti reflection coating in the polysilicon gate area (lines 39-49, ; Figs. 2B-2C); S4: injecting only an HBr gas into the etch chamber at a cure flow rate as an etch gas, to etch the bottom anti reflection coating (lines 12-35, column 4; Figs. 2B-2C); S5: etching the hard mask layer, to remove the hard mask layer not covered by the bottom anti reflection coating and retain the hard mask layer covered by the bottom anti reflection coating (lines 14-17, column 6); and S6: performing subsequent process steps to complete polysilicon gate etch (etching the reminder of the gate stack, lines 52-58, column 4).
Bell is silent about the limitation “so that the anti reflection coating and the photoresist in the polysilicon gate area are further narrowed, reducing a width difference between the anti reflection coatings on the polysilicon gates at various positions on the wafer”. However, this limitation in the method claim simply expresses intended use of the recited process. It does not provide a positive limitation for the method claim. Therefore, it is not accorded any patentable weight.
Regarding claim 3, Bell discloses wherein the etch gas injected into the etch chamber in step S3 comprises an HBr gas (lines 12-49, column 4).
Regarding claim 4, Bell discloses wherein the hard mask layer is composed of at least one silicon oxide layer and/or a silicon nitride layer (lines 53-55, column 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Bell et al. (US7005386) in view of Wayton et al. (US20030180559).
Regarding claim 5, Bell is silent about wherein components of the bottom anti reflection coating comprise a body film-forming resin capable of cross-linking, a thermo acid generator, a crosslinking agent, and an organic solvent. However, Bell discloses that the bottom anti reflection coating comprises an organic ARC layer (line 40, column 3). In addition, Huang teaches that a bottom antireflective coating formed on a gate stack comprises a body film-forming resin capable of cross-linking, a thermo acid generator, a crosslinking agent, and an organic solvent (paragraphs 0013-0015 and 0019). Therefore, it would have been obvious to one of ordinary skill, in the art before the effective filing date of the claimed invention, to use a known organic bottom anti reflection coating as taught by Wayton, in the method of Bell, with a reasonable expectation of success. It has been held that combining prior art elements according to known methods to yield predictable results is obvious. See MPEP 2143 I.(A).
Allowable Subject Matter
Claims 2 and 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the cited prior art of record, taken either alone or in combination, fails to disclose or render obvious a method wherein step S6 comprises the following steps: S61: performing hard mask layer cure etch to reduce the width of the hard mask layer at each polysilicon gate on the wafer by a corresponding magnitude, in the context of the instant claim.
Regarding claim 6, the cited prior art of record, taken either alone or in combination, fails to disclose or render obvious a method wherein the bottom anti reflection coating comprises the following raw materials in mass percentages: 5-15% of aryl-containing glycoluril oligomer solution, 0.5-15% of body resin, 0.1-5% of crosslinking agent, 0.1-1% of thermosensitive acid, and the organic solvent of the remaining amount; wherein the body resin comprises a light-absorbing functional group, a crosslinking functional group, and an auxiliary functional group, in the context of the instant claim.
Regarding claim 7, the cited prior art of record, taken either alone or in combination, fails to disclose or render obvious a method wherein in step S4, the cure flow rate is determined by selection based on the design linewidths of the polysilicon gates at various positions on the wafer, and a matrix table of a calibrated HBr gas flow rate and magnitudes of changes in linewidths of different structures after etch; and the matrix table of the HBr gas flow rate and the magnitudes of changes in linewidths of different structures after etch is calibrated by a DOE experiment method, in the context of the instant claim.
Regarding claim 8, the cited prior art of record, taken either alone or in combination, fails to disclose or render obvious a method wherein during step S4, when the cure flow rate of HBr is determined by selection, design linewidths of the polysilicon gates of various structures and at various positions on the wafer are collected before the bottom anti reflection coating is etched; during step S5, widths of the hard mask layer at the polysilicon gates of various structures on the wafer are collected after the hard mask layer is etched; a center design linewidth for the current process is determined based on the design linewidths of the polysilicon gates of various structures and at various positions on the wafer that are collected before the bottom anti reflection coating is etched and during step S4 and the widths of the hard mask layer at the polysilicon gates of various structures on the wafer that are collected after the hard mask layer is etched and during step S5; and the center design linewidth is used as a centerline to establish a process window for the process, in the context of the instant claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nallan et al. (US20040058517) discloses a method of etching a gate structure (abstract and Fig. 1). Parkinson et al. (“Increased Uniformity Control in a 45nm Polysilicon Gate Etch Process”, Proc. Of SPIE, vol. 7272, year 2009, paper#72721J) discusses using DOE for gate CD control (abstract). Tao et al. (US6156629) discloses a method of etching a gate stack comprising photoresist, bottom anti-reflective coating, a hard mask, polysilicon, and gate oxide (abstract and Figs. 1-4).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIONG-PING LU whose telephone number is (571) 270-1135. The examiner can normally be reached on M-F: 9:00am – 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua L Allen, can be reached at telephone number (571)270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form.
/JIONG-PING LU/
Primary Examiner, Art Unit 1713
Prosecution Insights