CTNF 18/778,988 CTNF 83806 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Embodiment of Fig. 1 (Claims 1-7,9-13, 14, 21--27) in the reply filed on 05/12/2026 is acknowledged. 08-06 AIA Claim 15 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/12/2026 . Information Disclosure Statement The information disclosure statement (IDS) submitted on 07/21/2024, 12/18/2024, 01/03/2025, 06/27/2025 and 04/01/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2 and 4 rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kim et al. (US 2011/0254069) . As for claim 1, Kim et al. disclose in Figs. 1-14 or 17-21 and the related text a memory device, comprising: a stack 100 comprising one or more memory cell layers including a first memory cell layer comprising a word line gate 230, a plurality of floating gates FG and a data storage layer 220 (Fig. 4-13); a plurality of channel vias SP extending vertically through the stack from a first end to a second end and including a first channel via 170/180 that comprises a semiconductor layer [0170]; and a source line 250 (electrically/thermally) coupling to the semiconductor layer through the first end (Fig. 13); and a bit line 270 coupling to the semiconductor layer through the second end (Fig. 13); wherein the plurality of floating gates FG includes a first floating gate that encircles the first channel via SP (Fig. 14) and is separated from the semiconductor layer 170/180 by a tunnel dielectric TIL; the word line gate 230 surrounds the plurality of floating gates FG (Fig. 14); and the data storage layer 220 extends between the word line gate 230 and the plurality of floating gates FG (Fig. 14). As for claim 2, Kim et al. disclose the memory device of claim 1, wherein the one or more memory cell layers comprise a plurality of memory cell layers (Fig. 14). As for claim 4, Kim et al. disclose the memory device of claim 1, further comprising: a semiconductor substrate 10 [0076]; wherein the stack is formed on the semiconductor substrate (Fig. 13-14); and the source line 250 couples to the semiconductor layer 170/180 through a heavily doped region 250 of the semiconductor substrate 10 (Fig. 13/14) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 3, 9-12 and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Fujil (US 2020/0303558) . As for claim 3, Kim et al. disclose the memory device of claim 1, wherein the data storage layer comprises dielectric material; and the semiconductor layer 170/180, the tunnel dielectric TIL, the first floating gate FG, the data storage layer. Kim et al. do not disclose the data storage layer comprises a ferroelectric layer; the word line gate form an MFMIS memory cell. Fujil teach in Fig. 1-2B and the related text data storage layer 18 comprises a ferroelectric layer ([0047]-[0048]); the word line gate form an MFMIS memory cell (Fig. 1, [0022] and [0071]). Kim et al. and Fujil are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kim et al. to include the limitations as taught by Fujil in order to improve the reliability of the memory (Fujil [0004]). As for claims 9 and 11, Kim et al. disclose in Figs. 17-21 and the related text a memory device, comprising: substrate 10 comprising a stack area 100 and via areas, wherein the via 105 areas are surrounded by the stack area (Fig. 17-21); memory cell layers interleaved with isolation layers 120 in a stack over the substrate 10 (Fig. 19); MFMIS memory cells comprising gate electrodes 230, data storage layers 220, floating gates FG, tunnel dielectrics 160, and channels 170/180 in the memory cell layers (Fig. 17-21); semiconductor structures SP extending through the memory cell layers and the isolation layers in the via areas (Fig. 17-21); wherein the gate electrodes 230, the data storage layers 220, and the floating gates FL are in the stack area (Fig. 17-21); the channels 170/180 are provided by the semiconductor structures (Fig. 17-21); and the tunnel dielectrics 160 are disposed between the floating gates FG and the channels (Fig. 17-21). Kim et al. do not explicitly teach the data storage layer 18 comprises a ferroelectric layer; and memory cell is an MFMIS memory cell; and a plurality of the gate electrodes are united into a single structure. Fujil teach in Fig. 1-3 and the related text data storage layer 18 comprises a ferroelectric layer ([0047]-[0048]); memory cell is an MFMIS memory cell (Fig. 1, [0022] and [0071]); and a plurality of the gate electrodes WL are united into a single structure (Fig. 2B). Kim et al. and Fujil are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kim et al. to include the limitations as taught by Fujil in order to improve the reliability of the memory (Fujil [0004]). As for claim 10, Kim et al. disclose the memory device of claim 9, wherein the (data storage/ferroelectric) layers 220 extend above and below the gate electrodes 230 within the stack area (Fig. 17-21). As for claim 12, Kim et al. disclose the memory device of claim 9, wherein the gate electrodes 230 and the floating gates are metal ([0088] and [0107]). As for claim 21, Kim et al. disclose the memory device of claim 1, further comprising a dummy via 250 extending vertically through the stack, wherein the word line gate 230 abuts and surrounds the dummy via 250 (Fig. 19). As for claim 22, Kim et al. disclose the memory device of claim 1, further comprising a dummy via 250 extending vertically through the stack, wherein the word line gate surrounds the dummy via (Fig. 19), and there are no floating gates between the word line gate and the dummy via (fig. 19). As for claim 23, Kim et al. disclose the memory device of claim 1, wherein the plurality of floating gates are conductive material. Kim et al. do not teach the conductive material includes tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), or nickel (Ni). It is convention and would have been obvious to one of ordinary skill in the art at the time the invention was provide to use tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), or nickel (Ni) as material of the conductive material in Kim et al., in order to provide suitable conductive material . 07-21-aia AIA Claim (s) 5-7 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Kim et al. (US 2010/0171163) . As for claims 5-6, Kim et al. disclose the memory device of claim 1, except a bit line-connection select gate layer between the one or more memory cell layers and the second end; wherein the bit line-connection select gate layer comprises a bit line-connection select gate that extends around the plurality of channel vias; and a source line-connection select gate layer between the one or more memory cell layers and the first end; wherein the source line-connection select gate layer comprises a source line- connection select gate that extends around the plurality of channel vias. Kim et al. teach in Figs. 1-4 and the related text a bit line-connection select gate layer 162 between the one or more memory cell layers and the second end (Fig. 2-4); wherein the bit line-connection select gate layer 162 comprises a bit line-connection select gate 162 that extends around the plurality of channel vias 165; and a source line-connection select gate layer 132 between the one or more memory cell layers and the first end (Figs. 2-4); wherein the source line-connection select gate layer 132 comprises a source line-connection select gate that extends around the plurality of channel vias 165. Kim et al. and Kim et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kim et al. to include the limitations as taught by Kim et al. in order to control electrical connections (Kim et al. [0030] and [0037]). As for claim 7, Kim et al. disclose the memory device of claim 5, wherein the bit line-connection select gate 162 comprises semiconductor material [0036]. Kim et al. do not disclose the semiconductor material is polysilicon. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use polysilicon as material of the bit line-connection select gate, in order to provide suitable semiconductor material. As for claim 26, Kim et al. disclose the memory device of claim 1, wherein the plurality of floating gates comprise polysilicon. Fujil teach in Fig. 1-3 and the related text a plurality of floating gates 16 comprise a metal nitride [0043]. Kim et al., Kim et al. and Fujil are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kim et al. to include the limitations as taught by Fujil, in order to allow the device storage charge . 07-21-aia AIA Claim (s) 24 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Fujil and Kim et al .. As for claim 24, Kim et al. disclose in Figs. 17-19 and the related text a memory device, comprising: a cylindrical channel structure SP vertically oriented over a semiconductor substrate 10 (fig. 19); and a stack 100 surrounding the cylindrical channel structure (Fig. 19) and separated from the cylindrical channel structure by a dielectric layer 160, wherein the stack comprises insulating layers 120 and, separated by the insulating layers, and a plurality of data storage layers 220; wherein the metal-ferroelectric-metal layers 220 together with the dielectric layer and the cylindrical channel structure form a string of metal-ferroelectric-metal-insulator- semiconductor memory cells (Figs. 3) for which the source line-connection select gate and the bit line-connection select gate provide access control. Kim et al. do not disclose a source line-connection select gate, and a bit line-connection select gate; the data storage layers are metal-ferroelectric-metal layers. As for claims 5-6, Kim et al. disclose the memory device of claim 1, except a bit line-connection select gate layer between the one or more memory cell layers and the second end; wherein the bit line-connection select gate layer comprises a bit line-connection select gate that extends around the plurality of channel vias; and a source line-connection select gate layer between the one or more memory cell layers and the first end; wherein the source line-connection select gate layer comprises a source line- connection select gate that extends around the plurality of channel vias. Kim et al. teach in Figs. 1-4 and the related text a bit line-connection select gate layer 162 between the one or more memory cell layers and the second end (Fig. 2-4); wherein the bit line-connection select gate layer 162 comprises a bit line-connection select gate 162 that extends around the plurality of channel vias 165; and a source line-connection select gate layer 132 between the one or more memory cell layers and the first end (Figs. 2-4); wherein the source line-connection select gate layer 132 comprises a source line-connection select gate that extends around the plurality of channel vias 165. Fujil teach in Fig. 1-2B and the related text data storage layer 18 comprises a ferroelectric layer ([0047]-[0048]). Kim et al., Kim et al. and Fujil are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kim et al. to include the limitations as taught by Fujil and Kim et al. in order to improve the reliability of the memory (Fujil [0004]) and to control electrical connections (Kim et al. [0030] and [0037]). As for claims 25 and 27, Kim et al. in view of Kim et al. and Fujil et al. disclose the memory device of claims 13 and 24, wherein the source line-connection select gate 132 and the bit line-connection select gate 162 comprise semiconductor material [0036]. Kim et al. do not disclose the semiconductor material is polysilicon. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use polysilicon as material of the bit line-connection select gate, in order to provide suitable semiconductor material. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRANG Q TRAN/Primary Examiner, Art Unit 2811 Application/Control Number: 18/778,988 Page 2 Art Unit: 2811 Application/Control Number: 18/778,988 Page 3 Art Unit: 2811 Application/Control Number: 18/778,988 Page 4 Art Unit: 2811 Application/Control Number: 18/778,988 Page 5 Art Unit: 2811 Application/Control Number: 18/778,988 Page 6 Art Unit: 2811 Application/Control Number: 18/778,988 Page 7 Art Unit: 2811 Application/Control Number: 18/778,988 Page 8 Art Unit: 2811 Application/Control Number: 18/778,988 Page 9 Art Unit: 2811 Application/Control Number: 18/778,988 Page 10 Art Unit: 2811 Application/Control Number: 18/778,988 Page 11 Art Unit: 2811
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